Simulation Results: uart

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 10 0.00
uart_smoke 1.412s 0.000us 0 10 0.00
csr_hw_reset 0 1 0.00
uart_csr_hw_reset 0.925s 0.000us 0 1 0.00
csr_rw 0 5 0.00
uart_csr_rw 0.913s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
uart_csr_bit_bash 1.411s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
uart_csr_aliasing 1.452s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
uart_csr_mem_rw_with_rand_reset 1.650s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
uart_csr_rw 0.913s 0.000us 0 5 0.00
uart_csr_aliasing 1.452s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 0 10 0.00
uart_tx_rx 0.945s 0.000us 0 10 0.00
parity 0 20 0.00
uart_smoke 1.412s 0.000us 0 10 0.00
uart_tx_rx 0.945s 0.000us 0 10 0.00
parity_error 0 20 0.00
uart_intr 1.688s 0.000us 0 10 0.00
uart_rx_parity_err 1.599s 0.000us 0 10 0.00
watermark 0 20 0.00
uart_tx_rx 0.945s 0.000us 0 10 0.00
uart_intr 1.688s 0.000us 0 10 0.00
fifo_full 0 10 0.00
uart_fifo_full 1.621s 0.000us 0 10 0.00
fifo_overflow 0 10 0.00
uart_fifo_overflow 1.390s 0.000us 0 10 0.00
fifo_reset 0 200 0.00
uart_fifo_reset 2.082s 0.000us 0 200 0.00
rx_frame_err 0 10 0.00
uart_intr 1.688s 0.000us 0 10 0.00
rx_break_err 0 10 0.00
uart_intr 1.688s 0.000us 0 10 0.00
rx_timeout 0 10 0.00
uart_intr 1.688s 0.000us 0 10 0.00
perf 0 10 0.00
uart_perf 1.506s 0.000us 0 10 0.00
sys_loopback 0 10 0.00
uart_loopback 1.398s 0.000us 0 10 0.00
line_loopback 0 10 0.00
uart_loopback 1.398s 0.000us 0 10 0.00
rx_noise_filter 0 10 0.00
uart_noise_filter 1.384s 0.000us 0 10 0.00
rx_start_bit_filter 0 10 0.00
uart_rx_start_bit_filter 1.664s 0.000us 0 10 0.00
tx_overide 0 10 0.00
uart_tx_ovrd 1.663s 0.000us 0 10 0.00
rx_oversample 0 10 0.00
uart_rx_oversample 1.674s 0.000us 0 10 0.00
long_b2b_transfer 0 10 0.00
uart_long_xfer_wo_dly 1.568s 0.000us 0 10 0.00
stress_all 0 10 0.00
uart_stress_all 0.142s 0.000us 0 10 0.00
alert_test 0 10 0.00
uart_alert_test 1.593s 0.000us 0 10 0.00
intr_test 0 10 0.00
uart_intr_test 0.945s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
uart_tl_errors 1.651s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
uart_tl_errors 1.651s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
uart_csr_hw_reset 0.925s 0.000us 0 1 0.00
uart_csr_rw 0.913s 0.000us 0 5 0.00
uart_csr_aliasing 1.452s 0.000us 0 1 0.00
uart_same_csr_outstanding 0.912s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
uart_csr_hw_reset 0.925s 0.000us 0 1 0.00
uart_csr_rw 0.913s 0.000us 0 5 0.00
uart_csr_aliasing 1.452s 0.000us 0 1 0.00
uart_same_csr_outstanding 0.912s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
uart_sec_cm 1.589s 0.000us 0 5 0.00
uart_tl_intg_err 1.684s 0.000us 0 25 0.00
sec_cm_bus_integrity 0 25 0.00
uart_tl_intg_err 1.684s 0.000us 0 25 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 20 0.00
uart_stress_all_with_rand_reset 2.132s 0.000us 0 20 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 453 test runs
uart_smoke 110020831412758764809288681824203679442706147623903212949642964108437455588301 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2271693773 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_smoke.2271693773 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_smoke.2271693773 -covoverwrite' seed=110020831412758764809288681824203679442706147623903212949642964108437455588301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110020831412758764809288681824203679442706147623903212949642964108437455588301 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 109251942350750803386067689665528259763725030051934483127350734234565239075151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2851828047 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_tx_rx.2851828047 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_tx_rx.2851828047 -covoverwrite' seed=109251942350750803386067689665528259763725030051934483127350734234565239075151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109251942350750803386067689665528259763725030051934483127350734234565239075151 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 10970566408194430303969506346615113199016079586501937058212419950589145561680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3645684304 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_fifo_full.3645684304 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_fifo_full.3645684304 -covoverwrite' seed=10970566408194430303969506346615113199016079586501937058212419950589145561680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10970566408194430303969506346615113199016079586501937058212419950589145561680 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 52893838835146610099380616848373065589889233652767973060742763527014672409432 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2756617048 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_fifo_overflow.2756617048 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_fifo_overflow.2756617048 -covoverwrite' seed=52893838835146610099380616848373065589889233652767973060742763527014672409432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52893838835146610099380616848373065589889233652767973060742763527014672409432 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 20133873350274764381332089424834632369928970455827382399268800179658618646666 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2726637706 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_fifo_reset.2726637706 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_fifo_reset.2726637706 -covoverwrite' seed=20133873350274764381332089424834632369928970455827382399268800179658618646666 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20133873350274764381332089424834632369928970455827382399268800179658618646666 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 28463541764875224264445021828903360149340645977000725447332724027281849258908 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=308351900 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_rx_oversample.308351900 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_rx_oversample.308351900 -covoverwrite' seed=28463541764875224264445021828903360149340645977000725447332724027281849258908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28463541764875224264445021828903360149340645977000725447332724027281849258908 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 73629268881502081829749136296934443515076695600422698460336935920724443756082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3542447666 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_intr.3542447666 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_intr.3542447666 -covoverwrite' seed=73629268881502081829749136296934443515076695600422698460336935920724443756082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73629268881502081829749136296934443515076695600422698460336935920724443756082 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 109351940322862885774034379048743656092928008058035144615781121604339100115984 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3517539344 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_noise_filter.3517539344 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_noise_filter.3517539344 -covoverwrite' seed=109351940322862885774034379048743656092928008058035144615781121604339100115984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109351940322862885774034379048743656092928008058035144615781121604339100115984 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 38977388745133161621390730240471540337729558421223084055210093365407454314623 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=973586559 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_rx_start_bit_filter.973586559 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_rx_start_bit_filter.973586559 -covoverwrite' seed=38977388745133161621390730240471540337729558421223084055210093365407454314623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38977388745133161621390730240471540337729558421223084055210093365407454314623 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 112029914720164470919402145473452696478792787411777829329292865248350492500571 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2890474075 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_rx_parity_err.2890474075 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_rx_parity_err.2890474075 -covoverwrite' seed=112029914720164470919402145473452696478792787411777829329292865248350492500571 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112029914720164470919402145473452696478792787411777829329292865248350492500571 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 76750693549214039741297398183182024349799044778670522910459695594229135704746 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2390622890 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_tx_ovrd.2390622890 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_tx_ovrd.2390622890 -covoverwrite' seed=76750693549214039741297398183182024349799044778670522910459695594229135704746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76750693549214039741297398183182024349799044778670522910459695594229135704746 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 63268912747210934891143092994466765906234221033710377916202654820184502923442 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2071294130 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_loopback.2071294130 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_loopback.2071294130 -covoverwrite' seed=63268912747210934891143092994466765906234221033710377916202654820184502923442 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63268912747210934891143092994466765906234221033710377916202654820184502923442 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 97280001293802886793651211024882655130649881279601628422834942206541712518413 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=995814669 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_perf.995814669 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_perf.995814669 -covoverwrite' seed=97280001293802886793651211024882655130649881279601628422834942206541712518413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97280001293802886793651211024882655130649881279601628422834942206541712518413 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 68132501777873084702971031158149488381465162334968384437296416163735008657228 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=475479884 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_long_xfer_wo_dly.475479884 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_long_xfer_wo_dly.475479884 -covoverwrite' seed=68132501777873084702971031158149488381465162334968384437296416163735008657228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68132501777873084702971031158149488381465162334968384437296416163735008657228 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 12270092168297314576401838200874250475512152704652829407149540379303681564372 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2994577108 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_stress_all_with_rand_reset.2994577108 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_stress_all_with_rand_reset.2994577108 -covoverwrite' seed=12270092168297314576401838200874250475512152704652829407149540379303681564372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12270092168297314576401838200874250475512152704652829407149540379303681564372 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 79716462399015054847390215270722559686514472250759976687790801070021644466672 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3863820784 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_stress_all.3863820784 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_stress_all.3863820784 -covoverwrite' seed=79716462399015054847390215270722559686514472250759976687790801070021644466672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79716462399015054847390215270722559686514472250759976687790801070021644466672 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_sec_cm 22334438804319076456965494388479290945301358376241874452487410420025492362034 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1206506290 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_sec_cm.1206506290 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_sec_cm.1206506290 -covoverwrite' seed=22334438804319076456965494388479290945301358376241874452487410420025492362034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22334438804319076456965494388479290945301358376241874452487410420025492362034 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 15761802539023923844840840994489998756685997954021848768279448840547643231555 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3238858051 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_tl_errors.3238858051 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_tl_errors.3238858051 -covoverwrite' seed=15761802539023923844840840994489998756685997954021848768279448840547643231555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15761802539023923844840840994489998756685997954021848768279448840547643231555 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 413268881941591334957126547929574721710687766973705697709083644923736709264 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3509278864 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_tl_intg_err.3509278864 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_tl_intg_err.3509278864 -covoverwrite' seed=413268881941591334957126547929574721710687766973705697709083644923736709264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=413268881941591334957126547929574721710687766973705697709083644923736709264 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 28013665057709261450892899860207833929554896217082270451202358805074746405740 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=648409964 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_intr_test.648409964 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_intr_test.648409964 -covoverwrite' seed=28013665057709261450892899860207833929554896217082270451202358805074746405740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28013665057709261450892899860207833929554896217082270451202358805074746405740 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 68036537618443336831073710705239249691902828774113691564872314465106885536586 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1581968202 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/0.uart_alert_test.1581968202 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 0.uart_alert_test.1581968202 -covoverwrite' seed=68036537618443336831073710705239249691902828774113691564872314465106885536586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68036537618443336831073710705239249691902828774113691564872314465106885536586 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_hw_reset 96123550948130750264375523135127468676844790285281906046265823881314213248701 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2819047101 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_csr_hw_reset.2819047101 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_csr_hw_reset.2819047101 -covoverwrite' seed=96123550948130750264375523135127468676844790285281906046265823881314213248701 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96123550948130750264375523135127468676844790285281906046265823881314213248701 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_rw 100959960719483912190520380709529184437855525555037777522874813270855231088874 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=249702634 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_csr_rw.249702634 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_csr_rw.249702634 -covoverwrite' seed=100959960719483912190520380709529184437855525555037777522874813270855231088874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100959960719483912190520380709529184437855525555037777522874813270855231088874 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_bit_bash 3660695568259152781153295645238768734541249014009127234050384798795228318278 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3797748294 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_csr_bit_bash.3797748294 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_csr_bit_bash.3797748294 -covoverwrite' seed=3660695568259152781153295645238768734541249014009127234050384798795228318278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3660695568259152781153295645238768734541249014009127234050384798795228318278 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_aliasing 10707467434717429910399867877201437544392508412178835531185193137491272486843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2554286011 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_csr_aliasing.2554286011 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_csr_aliasing.2554286011 -covoverwrite' seed=10707467434717429910399867877201437544392508412178835531185193137491272486843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10707467434717429910399867877201437544392508412178835531185193137491272486843 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_same_csr_outstanding 88252353628592379126941807667308220991040021836683218056595176655285861820912 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3152620016 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_same_csr_outstanding.3152620016 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_same_csr_outstanding.3152620016 -covoverwrite' seed=88252353628592379126941807667308220991040021836683218056595176655285861820912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88252353628592379126941807667308220991040021836683218056595176655285861820912 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_mem_rw_with_rand_reset 113047824365935962049468700657714885132249080099481748689897097210792943120227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1136226147 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/0.uart_csr_mem_rw_with_rand_reset.1136226147 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.uart_csr_mem_rw_with_rand_reset.1136226147 -covoverwrite' seed=113047824365935962049468700657714885132249080099481748689897097210792943120227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113047824365935962049468700657714885132249080099481748689897097210792943120227 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/0.uart_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 53794624160269068858460124918674260076066803490071941860189523611636482544061 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1948357053 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_smoke.1948357053 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_smoke.1948357053 -covoverwrite' seed=53794624160269068858460124918674260076066803490071941860189523611636482544061 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53794624160269068858460124918674260076066803490071941860189523611636482544061 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 65465292833031377947218256179046238560045738324624446977238883410829158833815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=878108311 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_tx_rx.878108311 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_tx_rx.878108311 -covoverwrite' seed=65465292833031377947218256179046238560045738324624446977238883410829158833815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65465292833031377947218256179046238560045738324624446977238883410829158833815 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 63122571816006541984126642288842037622065786197744147068870513623751087705266 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2199997618 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_fifo_full.2199997618 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_fifo_full.2199997618 -covoverwrite' seed=63122571816006541984126642288842037622065786197744147068870513623751087705266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63122571816006541984126642288842037622065786197744147068870513623751087705266 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 33153837908643844124507850148545005468783784452773852349389360801958017780545 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1425951553 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_fifo_overflow.1425951553 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_fifo_overflow.1425951553 -covoverwrite' seed=33153837908643844124507850148545005468783784452773852349389360801958017780545 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33153837908643844124507850148545005468783784452773852349389360801958017780545 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 18493783674897897463084788890852054125083008297520862327323499263693975938839 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1748723479 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_fifo_reset.1748723479 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_fifo_reset.1748723479 -covoverwrite' seed=18493783674897897463084788890852054125083008297520862327323499263693975938839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18493783674897897463084788890852054125083008297520862327323499263693975938839 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 85071504396706239364909973604618112821403165703794309679101811554705779847849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2879517353 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_rx_oversample.2879517353 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_rx_oversample.2879517353 -covoverwrite' seed=85071504396706239364909973604618112821403165703794309679101811554705779847849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85071504396706239364909973604618112821403165703794309679101811554705779847849 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 113739180402063746163555837339245843128619359392409458357623642557544556300865 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=847415873 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_intr.847415873 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_intr.847415873 -covoverwrite' seed=113739180402063746163555837339245843128619359392409458357623642557544556300865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113739180402063746163555837339245843128619359392409458357623642557544556300865 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 16439310859314631446180233797690169222654685954031855874116061063011539735539 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2119029747 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_noise_filter.2119029747 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_noise_filter.2119029747 -covoverwrite' seed=16439310859314631446180233797690169222654685954031855874116061063011539735539 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16439310859314631446180233797690169222654685954031855874116061063011539735539 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 93448728261027414970137184079664952699242224573090403572372055877512459167063 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=517973335 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_rx_start_bit_filter.517973335 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_rx_start_bit_filter.517973335 -covoverwrite' seed=93448728261027414970137184079664952699242224573090403572372055877512459167063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93448728261027414970137184079664952699242224573090403572372055877512459167063 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 92398696490999580780674977003686710099568190370537558063688256025238002187525 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2965880069 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_rx_parity_err.2965880069 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_rx_parity_err.2965880069 -covoverwrite' seed=92398696490999580780674977003686710099568190370537558063688256025238002187525 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92398696490999580780674977003686710099568190370537558063688256025238002187525 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 95846947796446575990481334398407192376208344533747889658324293859908142112960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4049215680 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_tx_ovrd.4049215680 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_tx_ovrd.4049215680 -covoverwrite' seed=95846947796446575990481334398407192376208344533747889658324293859908142112960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95846947796446575990481334398407192376208344533747889658324293859908142112960 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 3667235093572254525990059160842660503536190822932293127353558609994096583166 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=559948286 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_loopback.559948286 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_loopback.559948286 -covoverwrite' seed=3667235093572254525990059160842660503536190822932293127353558609994096583166 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3667235093572254525990059160842660503536190822932293127353558609994096583166 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 69882964651766181398619624280470331235499530769642939208032143500434117317864 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3660403944 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_perf.3660403944 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_perf.3660403944 -covoverwrite' seed=69882964651766181398619624280470331235499530769642939208032143500434117317864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69882964651766181398619624280470331235499530769642939208032143500434117317864 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 25378494384998277532754143293799038174686395779891348787031422351618419551323 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3912330331 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_long_xfer_wo_dly.3912330331 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_long_xfer_wo_dly.3912330331 -covoverwrite' seed=25378494384998277532754143293799038174686395779891348787031422351618419551323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25378494384998277532754143293799038174686395779891348787031422351618419551323 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 68251450324099965850622418667835717247218476553792720088475923827682318951815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3554092423 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_stress_all_with_rand_reset.3554092423 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_stress_all_with_rand_reset.3554092423 -covoverwrite' seed=68251450324099965850622418667835717247218476553792720088475923827682318951815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68251450324099965850622418667835717247218476553792720088475923827682318951815 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 81946662465300138679306925459383672012471925342478177411342757831555620259809 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3956000737 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_stress_all.3956000737 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_stress_all.3956000737 -covoverwrite' seed=81946662465300138679306925459383672012471925342478177411342757831555620259809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81946662465300138679306925459383672012471925342478177411342757831555620259809 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_sec_cm 61454183443375145568388887301007454779142398530137798389382448135618068867416 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4236896600 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_sec_cm.4236896600 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_sec_cm.4236896600 -covoverwrite' seed=61454183443375145568388887301007454779142398530137798389382448135618068867416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61454183443375145568388887301007454779142398530137798389382448135618068867416 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 68167835653134977006997754890422875316128512754132612285776889844952091638991 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=903396559 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/1.uart_tl_errors.903396559 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.uart_tl_errors.903396559 -covoverwrite' seed=68167835653134977006997754890422875316128512754132612285776889844952091638991 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68167835653134977006997754890422875316128512754132612285776889844952091638991 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 110577008199484094425588321810404734687483509237887569999535062947381699736678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3944543334 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/1.uart_tl_intg_err.3944543334 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.uart_tl_intg_err.3944543334 -covoverwrite' seed=110577008199484094425588321810404734687483509237887569999535062947381699736678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110577008199484094425588321810404734687483509237887569999535062947381699736678 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 36731847712692707506824422070339649719180470432138663293159915839092695166976 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=985591808 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/1.uart_intr_test.985591808 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.uart_intr_test.985591808 -covoverwrite' seed=36731847712692707506824422070339649719180470432138663293159915839092695166976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36731847712692707506824422070339649719180470432138663293159915839092695166976 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 30219952255023664411862146022142401073122487637763377552002140248374877146508 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2376650124 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/1.uart_alert_test.2376650124 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 1.uart_alert_test.2376650124 -covoverwrite' seed=30219952255023664411862146022142401073122487637763377552002140248374877146508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30219952255023664411862146022142401073122487637763377552002140248374877146508 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_rw 62288755847037042057274720770540832260408885039610475264103111619045355726272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1708434880 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/1.uart_csr_rw.1708434880 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.uart_csr_rw.1708434880 -covoverwrite' seed=62288755847037042057274720770540832260408885039610475264103111619045355726272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62288755847037042057274720770540832260408885039610475264103111619045355726272 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_same_csr_outstanding 25061936152299293974839970697847139973464396814219934991995784341709731333185 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3826975809 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/1.uart_same_csr_outstanding.3826975809 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.uart_same_csr_outstanding.3826975809 -covoverwrite' seed=25061936152299293974839970697847139973464396814219934991995784341709731333185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25061936152299293974839970697847139973464396814219934991995784341709731333185 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_mem_rw_with_rand_reset 56583583625938770278787438197753044705662736696379998737057763129378344310897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2814679153 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/1.uart_csr_mem_rw_with_rand_reset.2814679153 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.uart_csr_mem_rw_with_rand_reset.2814679153 -covoverwrite' seed=56583583625938770278787438197753044705662736696379998737057763129378344310897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56583583625938770278787438197753044705662736696379998737057763129378344310897 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/1.uart_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 109824151661593592603310717436146184591717211617812300677917890248183522140668 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3071943164 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_smoke.3071943164 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_smoke.3071943164 -covoverwrite' seed=109824151661593592603310717436146184591717211617812300677917890248183522140668 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109824151661593592603310717436146184591717211617812300677917890248183522140668 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 64285323182721730000966470776609069533974069704725681428202267887115883299755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=931709867 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_tx_rx.931709867 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_tx_rx.931709867 -covoverwrite' seed=64285323182721730000966470776609069533974069704725681428202267887115883299755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64285323182721730000966470776609069533974069704725681428202267887115883299755 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 92468325660960203229339370105005821373112866938515430866168562680237289921897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1789681001 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_fifo_full.1789681001 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_fifo_full.1789681001 -covoverwrite' seed=92468325660960203229339370105005821373112866938515430866168562680237289921897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92468325660960203229339370105005821373112866938515430866168562680237289921897 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 88003950482606246819943251022134190799955778468982718952024776540985585227590 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2444678982 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_fifo_overflow.2444678982 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_fifo_overflow.2444678982 -covoverwrite' seed=88003950482606246819943251022134190799955778468982718952024776540985585227590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88003950482606246819943251022134190799955778468982718952024776540985585227590 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 108531897548368124146371438443814699253957995745181290440452215938487147867980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3445141324 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_fifo_reset.3445141324 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_fifo_reset.3445141324 -covoverwrite' seed=108531897548368124146371438443814699253957995745181290440452215938487147867980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108531897548368124146371438443814699253957995745181290440452215938487147867980 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 66171905439090413438330047489117667149083016106221199577957252748347911089602 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4249005506 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_rx_oversample.4249005506 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_rx_oversample.4249005506 -covoverwrite' seed=66171905439090413438330047489117667149083016106221199577957252748347911089602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66171905439090413438330047489117667149083016106221199577957252748347911089602 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 19679977447514308012415642865268156479598953867599092746063713892411602361884 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=356769308 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_intr.356769308 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_intr.356769308 -covoverwrite' seed=19679977447514308012415642865268156479598953867599092746063713892411602361884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19679977447514308012415642865268156479598953867599092746063713892411602361884 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 97300970614516614392174709029919924140121667982444764839131994784836863541146 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2143174554 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_noise_filter.2143174554 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_noise_filter.2143174554 -covoverwrite' seed=97300970614516614392174709029919924140121667982444764839131994784836863541146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97300970614516614392174709029919924140121667982444764839131994784836863541146 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 112340807401935310534294678099682324983273622089392525796707417402435650959680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4043815232 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_rx_start_bit_filter.4043815232 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_rx_start_bit_filter.4043815232 -covoverwrite' seed=112340807401935310534294678099682324983273622089392525796707417402435650959680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112340807401935310534294678099682324983273622089392525796707417402435650959680 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 67086647282376273510697325788836826721184943709038511829592928015595657249092 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2274115908 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_rx_parity_err.2274115908 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_rx_parity_err.2274115908 -covoverwrite' seed=67086647282376273510697325788836826721184943709038511829592928015595657249092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67086647282376273510697325788836826721184943709038511829592928015595657249092 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 9570598348349907178707353188220603076368138330265666650370341033891049436467 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=254211379 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_tx_ovrd.254211379 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_tx_ovrd.254211379 -covoverwrite' seed=9570598348349907178707353188220603076368138330265666650370341033891049436467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9570598348349907178707353188220603076368138330265666650370341033891049436467 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 90260134715516758194447371712904312345624730010126848976446386798379271062980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4267574724 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_loopback.4267574724 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_loopback.4267574724 -covoverwrite' seed=90260134715516758194447371712904312345624730010126848976446386798379271062980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90260134715516758194447371712904312345624730010126848976446386798379271062980 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 95785150626878214541621540007247470593371567767121619568511385393577781905580 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2365868204 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_perf.2365868204 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_perf.2365868204 -covoverwrite' seed=95785150626878214541621540007247470593371567767121619568511385393577781905580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95785150626878214541621540007247470593371567767121619568511385393577781905580 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 8124807813491041720848604158931821409727861944779270365662997970154537801792 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2053298240 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_long_xfer_wo_dly.2053298240 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_long_xfer_wo_dly.2053298240 -covoverwrite' seed=8124807813491041720848604158931821409727861944779270365662997970154537801792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8124807813491041720848604158931821409727861944779270365662997970154537801792 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 16862084980427663542794356981441544890511020671223125067928329890152976680546 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=712181346 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_stress_all_with_rand_reset.712181346 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_stress_all_with_rand_reset.712181346 -covoverwrite' seed=16862084980427663542794356981441544890511020671223125067928329890152976680546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16862084980427663542794356981441544890511020671223125067928329890152976680546 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 90836365560368095394958769368971220718276184956564324309097212831252874057542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2695681862 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_stress_all.2695681862 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_stress_all.2695681862 -covoverwrite' seed=90836365560368095394958769368971220718276184956564324309097212831252874057542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90836365560368095394958769368971220718276184956564324309097212831252874057542 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_sec_cm 123704708326017194503796068713412061402120901124593322321872418599181338728 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1984546920 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_sec_cm.1984546920 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_sec_cm.1984546920 -covoverwrite' seed=123704708326017194503796068713412061402120901124593322321872418599181338728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=123704708326017194503796068713412061402120901124593322321872418599181338728 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 103158991929267936436993069158969092747507477673616281094923382028330920116437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2884436181 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/2.uart_tl_errors.2884436181 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.uart_tl_errors.2884436181 -covoverwrite' seed=103158991929267936436993069158969092747507477673616281094923382028330920116437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103158991929267936436993069158969092747507477673616281094923382028330920116437 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 52834488212104098205658290758132664469448126482139694683243335277023877209836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=207167212 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/2.uart_tl_intg_err.207167212 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.uart_tl_intg_err.207167212 -covoverwrite' seed=52834488212104098205658290758132664469448126482139694683243335277023877209836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52834488212104098205658290758132664469448126482139694683243335277023877209836 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 52141158787705217024451675202767028880922007943770727391893879818595686523030 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2749472918 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/2.uart_intr_test.2749472918 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.uart_intr_test.2749472918 -covoverwrite' seed=52141158787705217024451675202767028880922007943770727391893879818595686523030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52141158787705217024451675202767028880922007943770727391893879818595686523030 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 47255797016512826131656990951135928000977855645195445613012655317395630823930 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3364198906 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/2.uart_alert_test.3364198906 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 2.uart_alert_test.3364198906 -covoverwrite' seed=47255797016512826131656990951135928000977855645195445613012655317395630823930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47255797016512826131656990951135928000977855645195445613012655317395630823930 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_rw 27426933488076512068547121128465736335452522592584759345656735639329458285493 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=537586613 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/2.uart_csr_rw.537586613 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.uart_csr_rw.537586613 -covoverwrite' seed=27426933488076512068547121128465736335452522592584759345656735639329458285493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27426933488076512068547121128465736335452522592584759345656735639329458285493 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_same_csr_outstanding 71689957615471712733972642627321753743960110876102113268316202203596842685946 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3389871610 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/2.uart_same_csr_outstanding.3389871610 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.uart_same_csr_outstanding.3389871610 -covoverwrite' seed=71689957615471712733972642627321753743960110876102113268316202203596842685946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71689957615471712733972642627321753743960110876102113268316202203596842685946 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_mem_rw_with_rand_reset 78611461294829290419076025798716774165511637547155853538674990575414392198106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2426213338 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/2.uart_csr_mem_rw_with_rand_reset.2426213338 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.uart_csr_mem_rw_with_rand_reset.2426213338 -covoverwrite' seed=78611461294829290419076025798716774165511637547155853538674990575414392198106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78611461294829290419076025798716774165511637547155853538674990575414392198106 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/2.uart_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 78975155293105481426751246831743640153792050529667204937834945118631006699786 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1596588298 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_smoke.1596588298 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_smoke.1596588298 -covoverwrite' seed=78975155293105481426751246831743640153792050529667204937834945118631006699786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78975155293105481426751246831743640153792050529667204937834945118631006699786 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 43380369510033267053923715769880688873331078332562243268668482869086522701040 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=849605872 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_tx_rx.849605872 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_tx_rx.849605872 -covoverwrite' seed=43380369510033267053923715769880688873331078332562243268668482869086522701040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43380369510033267053923715769880688873331078332562243268668482869086522701040 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 86341334533958558776926875762692739531377505856862123557256859209163203892319 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3517404255 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_fifo_full.3517404255 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_fifo_full.3517404255 -covoverwrite' seed=86341334533958558776926875762692739531377505856862123557256859209163203892319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86341334533958558776926875762692739531377505856862123557256859209163203892319 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 58192690510755161221390866738867260824557127004941968724091501328819532457498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1760683546 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_fifo_overflow.1760683546 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_fifo_overflow.1760683546 -covoverwrite' seed=58192690510755161221390866738867260824557127004941968724091501328819532457498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58192690510755161221390866738867260824557127004941968724091501328819532457498 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 83471579521604028621294346353457782013714230521297083094917814138888705095363 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1846359747 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_fifo_reset.1846359747 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_fifo_reset.1846359747 -covoverwrite' seed=83471579521604028621294346353457782013714230521297083094917814138888705095363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83471579521604028621294346353457782013714230521297083094917814138888705095363 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 71843028583030780647582104329636629293609712386282674111152186023522004608169 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=968074409 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_rx_oversample.968074409 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_rx_oversample.968074409 -covoverwrite' seed=71843028583030780647582104329636629293609712386282674111152186023522004608169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71843028583030780647582104329636629293609712386282674111152186023522004608169 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 25154519125005236513468651549610032330002279789111968681699670768658856845151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2068619103 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_intr.2068619103 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_intr.2068619103 -covoverwrite' seed=25154519125005236513468651549610032330002279789111968681699670768658856845151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25154519125005236513468651549610032330002279789111968681699670768658856845151 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 48841065089074711560715360493414981996806231019898600321766246039785355162649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2190291993 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_noise_filter.2190291993 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_noise_filter.2190291993 -covoverwrite' seed=48841065089074711560715360493414981996806231019898600321766246039785355162649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48841065089074711560715360493414981996806231019898600321766246039785355162649 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 12436591541926079235211311983526940253353845853809700899755517070921072567330 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2047009826 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_rx_start_bit_filter.2047009826 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_rx_start_bit_filter.2047009826 -covoverwrite' seed=12436591541926079235211311983526940253353845853809700899755517070921072567330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12436591541926079235211311983526940253353845853809700899755517070921072567330 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 41725660158100494228662562033364728985505059460913084222694298291538448586382 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4170421902 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_rx_parity_err.4170421902 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_rx_parity_err.4170421902 -covoverwrite' seed=41725660158100494228662562033364728985505059460913084222694298291538448586382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41725660158100494228662562033364728985505059460913084222694298291538448586382 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 76344012461221263296292567055575041741763729274332735171580175100408534705820 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1697425052 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_tx_ovrd.1697425052 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_tx_ovrd.1697425052 -covoverwrite' seed=76344012461221263296292567055575041741763729274332735171580175100408534705820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76344012461221263296292567055575041741763729274332735171580175100408534705820 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 22236768409718194412995441873954353460733224547264564379291670075786503853399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1018369367 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_loopback.1018369367 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_loopback.1018369367 -covoverwrite' seed=22236768409718194412995441873954353460733224547264564379291670075786503853399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22236768409718194412995441873954353460733224547264564379291670075786503853399 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 34730730824597069737257570948154205778068417169858103326005138868827130120243 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3274393651 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_perf.3274393651 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_perf.3274393651 -covoverwrite' seed=34730730824597069737257570948154205778068417169858103326005138868827130120243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34730730824597069737257570948154205778068417169858103326005138868827130120243 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 50347748349506907835405264402874291982494736345733366086828209385786651786719 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1637170655 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_long_xfer_wo_dly.1637170655 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_long_xfer_wo_dly.1637170655 -covoverwrite' seed=50347748349506907835405264402874291982494736345733366086828209385786651786719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50347748349506907835405264402874291982494736345733366086828209385786651786719 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 68445590177281508001385747259235019436536870975551319500362754510531148630116 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3612330084 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_stress_all_with_rand_reset.3612330084 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_stress_all_with_rand_reset.3612330084 -covoverwrite' seed=68445590177281508001385747259235019436536870975551319500362754510531148630116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68445590177281508001385747259235019436536870975551319500362754510531148630116 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 62577248819232363314185783581680326583294929231138465867933602954144960900726 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4069682806 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_stress_all.4069682806 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_stress_all.4069682806 -covoverwrite' seed=62577248819232363314185783581680326583294929231138465867933602954144960900726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62577248819232363314185783581680326583294929231138465867933602954144960900726 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_sec_cm 49938357808520737126630340528824409532388075805627818384241742006308894796710 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3991530406 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_sec_cm.3991530406 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_sec_cm.3991530406 -covoverwrite' seed=49938357808520737126630340528824409532388075805627818384241742006308894796710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49938357808520737126630340528824409532388075805627818384241742006308894796710 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 70004675028156607847931548613348622152575799779604383590809648062287241783070 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2250483486 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/3.uart_tl_errors.2250483486 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.uart_tl_errors.2250483486 -covoverwrite' seed=70004675028156607847931548613348622152575799779604383590809648062287241783070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70004675028156607847931548613348622152575799779604383590809648062287241783070 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 42658120881050165060422781802779083922421308108601302806564820668997835542700 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1211748524 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/3.uart_tl_intg_err.1211748524 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.uart_tl_intg_err.1211748524 -covoverwrite' seed=42658120881050165060422781802779083922421308108601302806564820668997835542700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42658120881050165060422781802779083922421308108601302806564820668997835542700 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 78400136405594594063642314042675075203184655360949489122208132414482087246682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3261954906 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/3.uart_intr_test.3261954906 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.uart_intr_test.3261954906 -covoverwrite' seed=78400136405594594063642314042675075203184655360949489122208132414482087246682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78400136405594594063642314042675075203184655360949489122208132414482087246682 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 69486968306521231442857610923582705660751656452108995744089289538215591166350 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4009378190 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/3.uart_alert_test.4009378190 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 3.uart_alert_test.4009378190 -covoverwrite' seed=69486968306521231442857610923582705660751656452108995744089289538215591166350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69486968306521231442857610923582705660751656452108995744089289538215591166350 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_rw 64941029891236993555122639640899496025815884217015169933084564006241985238979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3281131459 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/3.uart_csr_rw.3281131459 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.uart_csr_rw.3281131459 -covoverwrite' seed=64941029891236993555122639640899496025815884217015169933084564006241985238979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64941029891236993555122639640899496025815884217015169933084564006241985238979 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_same_csr_outstanding 86226450593723398307901098672193698452736298835291198219070873541339757996146 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2602362994 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/3.uart_same_csr_outstanding.2602362994 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.uart_same_csr_outstanding.2602362994 -covoverwrite' seed=86226450593723398307901098672193698452736298835291198219070873541339757996146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86226450593723398307901098672193698452736298835291198219070873541339757996146 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_mem_rw_with_rand_reset 70441209202151279555860218182892420239838513837865102051370912838305169662308 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3144278372 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/3.uart_csr_mem_rw_with_rand_reset.3144278372 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.uart_csr_mem_rw_with_rand_reset.3144278372 -covoverwrite' seed=70441209202151279555860218182892420239838513837865102051370912838305169662308 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70441209202151279555860218182892420239838513837865102051370912838305169662308 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/3.uart_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 33440549650834817762753554615263645176436602574321778011507731680416854902149 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=766182789 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_smoke.766182789 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_smoke.766182789 -covoverwrite' seed=33440549650834817762753554615263645176436602574321778011507731680416854902149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33440549650834817762753554615263645176436602574321778011507731680416854902149 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 44564013342439741826936185258712193396388529897697526213861568485525525034260 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3176330516 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_tx_rx.3176330516 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_tx_rx.3176330516 -covoverwrite' seed=44564013342439741826936185258712193396388529897697526213861568485525525034260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44564013342439741826936185258712193396388529897697526213861568485525525034260 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 30495669175209492320423131134496688383094576542761543174516710893039089496265 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=965357769 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_fifo_full.965357769 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_fifo_full.965357769 -covoverwrite' seed=30495669175209492320423131134496688383094576542761543174516710893039089496265 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30495669175209492320423131134496688383094576542761543174516710893039089496265 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 31188339828225036390987922106260260781315227803030267256071949541987834994818 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=469049474 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_fifo_overflow.469049474 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_fifo_overflow.469049474 -covoverwrite' seed=31188339828225036390987922106260260781315227803030267256071949541987834994818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31188339828225036390987922106260260781315227803030267256071949541987834994818 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 49493852223080525705611948252167483166543929152189387456398877276840841577238 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4186047254 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_fifo_reset.4186047254 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_fifo_reset.4186047254 -covoverwrite' seed=49493852223080525705611948252167483166543929152189387456398877276840841577238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49493852223080525705611948252167483166543929152189387456398877276840841577238 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 115308110086154744208910469444479236199095144401554683206687414010117536441357 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1514759181 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_rx_oversample.1514759181 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_rx_oversample.1514759181 -covoverwrite' seed=115308110086154744208910469444479236199095144401554683206687414010117536441357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115308110086154744208910469444479236199095144401554683206687414010117536441357 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 21948859417443404901574981563911254568613397661152371104405332503410563629275 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2926854363 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_intr.2926854363 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_intr.2926854363 -covoverwrite' seed=21948859417443404901574981563911254568613397661152371104405332503410563629275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21948859417443404901574981563911254568613397661152371104405332503410563629275 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 13284021296895082941758201780300806078432957951488722174799201215338290912755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2383191539 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_noise_filter.2383191539 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_noise_filter.2383191539 -covoverwrite' seed=13284021296895082941758201780300806078432957951488722174799201215338290912755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13284021296895082941758201780300806078432957951488722174799201215338290912755 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 73639281314678176610803837799588841718134629948711300178657785442746272096768 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2446893568 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_rx_start_bit_filter.2446893568 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_rx_start_bit_filter.2446893568 -covoverwrite' seed=73639281314678176610803837799588841718134629948711300178657785442746272096768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73639281314678176610803837799588841718134629948711300178657785442746272096768 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 98229642794107343346943416036770092950194339802829890792837264437440777842906 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=366244058 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_rx_parity_err.366244058 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_rx_parity_err.366244058 -covoverwrite' seed=98229642794107343346943416036770092950194339802829890792837264437440777842906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98229642794107343346943416036770092950194339802829890792837264437440777842906 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 3441451249528407311537526544978269685743422445843138217155242855153203476309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3015505749 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_tx_ovrd.3015505749 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_tx_ovrd.3015505749 -covoverwrite' seed=3441451249528407311537526544978269685743422445843138217155242855153203476309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3441451249528407311537526544978269685743422445843138217155242855153203476309 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 18214452383389198955681267493784079682028175592158825042975349509126614725285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4273779365 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_loopback.4273779365 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_loopback.4273779365 -covoverwrite' seed=18214452383389198955681267493784079682028175592158825042975349509126614725285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18214452383389198955681267493784079682028175592158825042975349509126614725285 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 91825704064765415365732479444919212824864297529550831928986266759607252320084 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=416972628 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_perf.416972628 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_perf.416972628 -covoverwrite' seed=91825704064765415365732479444919212824864297529550831928986266759607252320084 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91825704064765415365732479444919212824864297529550831928986266759607252320084 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 101221598040176105409768683665122521648795465387316172547404053015659118767186 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=788442194 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_long_xfer_wo_dly.788442194 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_long_xfer_wo_dly.788442194 -covoverwrite' seed=101221598040176105409768683665122521648795465387316172547404053015659118767186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101221598040176105409768683665122521648795465387316172547404053015659118767186 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 82014034976379742965260310294161508466346244407905901901698165356704943078706 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2284092722 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_stress_all_with_rand_reset.2284092722 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_stress_all_with_rand_reset.2284092722 -covoverwrite' seed=82014034976379742965260310294161508466346244407905901901698165356704943078706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82014034976379742965260310294161508466346244407905901901698165356704943078706 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 20825739890112494907499231228049249506231701698402019775211548363280969930568 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1524668232 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_stress_all.1524668232 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_stress_all.1524668232 -covoverwrite' seed=20825739890112494907499231228049249506231701698402019775211548363280969930568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20825739890112494907499231228049249506231701698402019775211548363280969930568 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_sec_cm 71639338830531289292666552438860674775759876854000561362145226722117053864330 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1620859274 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_sec_cm.1620859274 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_sec_cm.1620859274 -covoverwrite' seed=71639338830531289292666552438860674775759876854000561362145226722117053864330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71639338830531289292666552438860674775759876854000561362145226722117053864330 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 33362921995270359610607982078514881913423793589969019484967308618871280259656 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4259336776 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/4.uart_tl_errors.4259336776 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.uart_tl_errors.4259336776 -covoverwrite' seed=33362921995270359610607982078514881913423793589969019484967308618871280259656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33362921995270359610607982078514881913423793589969019484967308618871280259656 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 75584763969398040525455829886045334387192554330047954083733917144507867871127 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2690529175 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/4.uart_tl_intg_err.2690529175 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.uart_tl_intg_err.2690529175 -covoverwrite' seed=75584763969398040525455829886045334387192554330047954083733917144507867871127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75584763969398040525455829886045334387192554330047954083733917144507867871127 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 23712483032584498178743019787622089072360643784316902116666111558605414963234 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3893205026 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/4.uart_intr_test.3893205026 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.uart_intr_test.3893205026 -covoverwrite' seed=23712483032584498178743019787622089072360643784316902116666111558605414963234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23712483032584498178743019787622089072360643784316902116666111558605414963234 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 73412294751399417246422068745640513052920048880632476203864160604009887661786 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2503704282 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/4.uart_alert_test.2503704282 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 4.uart_alert_test.2503704282 -covoverwrite' seed=73412294751399417246422068745640513052920048880632476203864160604009887661786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73412294751399417246422068745640513052920048880632476203864160604009887661786 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_rw 9120295822289729350347759128230147611912714894766561594953282463142507476419 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2060481987 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/4.uart_csr_rw.2060481987 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.uart_csr_rw.2060481987 -covoverwrite' seed=9120295822289729350347759128230147611912714894766561594953282463142507476419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9120295822289729350347759128230147611912714894766561594953282463142507476419 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_same_csr_outstanding 76482131228143516332392793097555946488141837159931898836247665040018921559699 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1731794579 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/4.uart_same_csr_outstanding.1731794579 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.uart_same_csr_outstanding.1731794579 -covoverwrite' seed=76482131228143516332392793097555946488141837159931898836247665040018921559699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76482131228143516332392793097555946488141837159931898836247665040018921559699 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_csr_mem_rw_with_rand_reset 112025386348647845996327482699213276352874493320892736666416291888290623029626 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=57573754 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/4.uart_csr_mem_rw_with_rand_reset.57573754 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.uart_csr_mem_rw_with_rand_reset.57573754 -covoverwrite' seed=112025386348647845996327482699213276352874493320892736666416291888290623029626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112025386348647845996327482699213276352874493320892736666416291888290623029626 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/4.uart_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 27253475098709003510037592739187095477252021204654530083053275240564032922538 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2257183658 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_smoke.2257183658 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_smoke.2257183658 -covoverwrite' seed=27253475098709003510037592739187095477252021204654530083053275240564032922538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27253475098709003510037592739187095477252021204654530083053275240564032922538 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 62204664428355537907400758779871467005322845611887862302777202664972806776542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1976821470 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_tx_rx.1976821470 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_tx_rx.1976821470 -covoverwrite' seed=62204664428355537907400758779871467005322845611887862302777202664972806776542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62204664428355537907400758779871467005322845611887862302777202664972806776542 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 106133838951208311346203511539000828946225843574388669222649668113282118627743 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3400184223 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_fifo_full.3400184223 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_fifo_full.3400184223 -covoverwrite' seed=106133838951208311346203511539000828946225843574388669222649668113282118627743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106133838951208311346203511539000828946225843574388669222649668113282118627743 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 33611930699030479794535199479982144181655044166470781352087544776383056228956 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2249372252 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_fifo_overflow.2249372252 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_fifo_overflow.2249372252 -covoverwrite' seed=33611930699030479794535199479982144181655044166470781352087544776383056228956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33611930699030479794535199479982144181655044166470781352087544776383056228956 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 54781492253936773985873419440966319811272294254526718255600677150258897463564 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1927653644 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_fifo_reset.1927653644 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_fifo_reset.1927653644 -covoverwrite' seed=54781492253936773985873419440966319811272294254526718255600677150258897463564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54781492253936773985873419440966319811272294254526718255600677150258897463564 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 7508823646060369387886961855201446423110671919794538823203581486888435273518 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2640793390 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_rx_oversample.2640793390 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_rx_oversample.2640793390 -covoverwrite' seed=7508823646060369387886961855201446423110671919794538823203581486888435273518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7508823646060369387886961855201446423110671919794538823203581486888435273518 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 42737638305662541724723272630133275359121673768320338676530816507171699147337 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1396163145 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_intr.1396163145 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_intr.1396163145 -covoverwrite' seed=42737638305662541724723272630133275359121673768320338676530816507171699147337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42737638305662541724723272630133275359121673768320338676530816507171699147337 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 24858810174533758813279853316652330564579419683766338643104475420854514573352 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1051156520 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_noise_filter.1051156520 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_noise_filter.1051156520 -covoverwrite' seed=24858810174533758813279853316652330564579419683766338643104475420854514573352 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24858810174533758813279853316652330564579419683766338643104475420854514573352 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 61855961547446515554415806073543430210783747568860868318033776421805374031205 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=332645733 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_rx_start_bit_filter.332645733 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_rx_start_bit_filter.332645733 -covoverwrite' seed=61855961547446515554415806073543430210783747568860868318033776421805374031205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61855961547446515554415806073543430210783747568860868318033776421805374031205 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 91658182627532507149772417258608207625364018414448827327796633972799651177849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1959257465 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_rx_parity_err.1959257465 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_rx_parity_err.1959257465 -covoverwrite' seed=91658182627532507149772417258608207625364018414448827327796633972799651177849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91658182627532507149772417258608207625364018414448827327796633972799651177849 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 106601451456245271000316554215811717332949606409851530553799075033456758693379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=723197443 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_tx_ovrd.723197443 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_tx_ovrd.723197443 -covoverwrite' seed=106601451456245271000316554215811717332949606409851530553799075033456758693379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106601451456245271000316554215811717332949606409851530553799075033456758693379 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 69162090191375066962346256742594928204914553038359301481214711218688555313093 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1714251717 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_loopback.1714251717 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_loopback.1714251717 -covoverwrite' seed=69162090191375066962346256742594928204914553038359301481214711218688555313093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69162090191375066962346256742594928204914553038359301481214711218688555313093 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 90401936525282311785288699434928797455004314606073899882743735511391339984331 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2324608459 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_perf.2324608459 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_perf.2324608459 -covoverwrite' seed=90401936525282311785288699434928797455004314606073899882743735511391339984331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90401936525282311785288699434928797455004314606073899882743735511391339984331 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 27184975118170270427800445495323877931564815433900574928373788630599589655196 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3795808924 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_long_xfer_wo_dly.3795808924 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_long_xfer_wo_dly.3795808924 -covoverwrite' seed=27184975118170270427800445495323877931564815433900574928373788630599589655196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27184975118170270427800445495323877931564815433900574928373788630599589655196 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 39046923985663404254066712951682898509409963203420696952571038117622827497696 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4284266720 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_stress_all_with_rand_reset.4284266720 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_stress_all_with_rand_reset.4284266720 -covoverwrite' seed=39046923985663404254066712951682898509409963203420696952571038117622827497696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39046923985663404254066712951682898509409963203420696952571038117622827497696 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 62474785454987288310037740825712375186577871372483286952780475799000685852477 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=302888765 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_stress_all.302888765 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_stress_all.302888765 -covoverwrite' seed=62474785454987288310037740825712375186577871372483286952780475799000685852477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62474785454987288310037740825712375186577871372483286952780475799000685852477 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 44175858684319851897347211733083431719468969220679198483146119836554700887221 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2264241333 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/5.uart_tl_errors.2264241333 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.uart_tl_errors.2264241333 -covoverwrite' seed=44175858684319851897347211733083431719468969220679198483146119836554700887221 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44175858684319851897347211733083431719468969220679198483146119836554700887221 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 32982109555789113307779056273953469830631410356136821056669841554071699843105 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3880249377 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/5.uart_tl_intg_err.3880249377 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.uart_tl_intg_err.3880249377 -covoverwrite' seed=32982109555789113307779056273953469830631410356136821056669841554071699843105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32982109555789113307779056273953469830631410356136821056669841554071699843105 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 110534765976133458664030449449835290842142955742862743845074909960375783171853 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=776251149 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/5.uart_intr_test.776251149 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.uart_intr_test.776251149 -covoverwrite' seed=110534765976133458664030449449835290842142955742862743845074909960375783171853 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110534765976133458664030449449835290842142955742862743845074909960375783171853 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 50149029433345526937476176691620947295292802593102413096396012664321222858564 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3883882308 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/5.uart_alert_test.3883882308 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 5.uart_alert_test.3883882308 -covoverwrite' seed=50149029433345526937476176691620947295292802593102413096396012664321222858564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50149029433345526937476176691620947295292802593102413096396012664321222858564 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/5.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 109991182401752685813199211358547019620755290685616614427509253391563966138842 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3153873370 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_smoke.3153873370 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_smoke.3153873370 -covoverwrite' seed=109991182401752685813199211358547019620755290685616614427509253391563966138842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109991182401752685813199211358547019620755290685616614427509253391563966138842 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 29724325431052792731267427323465659928262489356283531309653197618078035083000 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1789787896 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_tx_rx.1789787896 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_tx_rx.1789787896 -covoverwrite' seed=29724325431052792731267427323465659928262489356283531309653197618078035083000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29724325431052792731267427323465659928262489356283531309653197618078035083000 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 8543479598211782613755860852120088539045439001421108148093547256621874155579 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3147698235 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_fifo_full.3147698235 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_fifo_full.3147698235 -covoverwrite' seed=8543479598211782613755860852120088539045439001421108148093547256621874155579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8543479598211782613755860852120088539045439001421108148093547256621874155579 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 49668551709923488748208119490133288353875565558372316611084425809842183942723 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1106063939 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_fifo_overflow.1106063939 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_fifo_overflow.1106063939 -covoverwrite' seed=49668551709923488748208119490133288353875565558372316611084425809842183942723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49668551709923488748208119490133288353875565558372316611084425809842183942723 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 86054342208552085455984109969908849437995499632532575202739495927497122838149 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4215731845 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_fifo_reset.4215731845 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_fifo_reset.4215731845 -covoverwrite' seed=86054342208552085455984109969908849437995499632532575202739495927497122838149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86054342208552085455984109969908849437995499632532575202739495927497122838149 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 88226179921526843747596194899357592275632130521862881241662432752401969315454 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1028390526 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_rx_oversample.1028390526 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_rx_oversample.1028390526 -covoverwrite' seed=88226179921526843747596194899357592275632130521862881241662432752401969315454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88226179921526843747596194899357592275632130521862881241662432752401969315454 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 33779525597564983579018577693900338878484358598707543082062610024429976591663 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1032363311 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_intr.1032363311 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_intr.1032363311 -covoverwrite' seed=33779525597564983579018577693900338878484358598707543082062610024429976591663 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33779525597564983579018577693900338878484358598707543082062610024429976591663 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 91930374823265990709135654199708883498648228722178786451789608357234021448591 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2608282511 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_noise_filter.2608282511 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_noise_filter.2608282511 -covoverwrite' seed=91930374823265990709135654199708883498648228722178786451789608357234021448591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91930374823265990709135654199708883498648228722178786451789608357234021448591 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 15854197416281128368145682555132909305534882941254761969325238581843379045905 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1594574353 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_rx_start_bit_filter.1594574353 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_rx_start_bit_filter.1594574353 -covoverwrite' seed=15854197416281128368145682555132909305534882941254761969325238581843379045905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15854197416281128368145682555132909305534882941254761969325238581843379045905 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 19270957511057339185174488157569502311860751338552284616167275863259347768286 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2067616734 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_rx_parity_err.2067616734 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_rx_parity_err.2067616734 -covoverwrite' seed=19270957511057339185174488157569502311860751338552284616167275863259347768286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19270957511057339185174488157569502311860751338552284616167275863259347768286 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 6330112336597096604686459797164628188972791369503428613545494537390690098463 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2973719839 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_tx_ovrd.2973719839 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_tx_ovrd.2973719839 -covoverwrite' seed=6330112336597096604686459797164628188972791369503428613545494537390690098463 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6330112336597096604686459797164628188972791369503428613545494537390690098463 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 76730627977767234242792800147901473641006644502588332994701730947734167351406 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1585442926 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_loopback.1585442926 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_loopback.1585442926 -covoverwrite' seed=76730627977767234242792800147901473641006644502588332994701730947734167351406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76730627977767234242792800147901473641006644502588332994701730947734167351406 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 112641230111156602525400529379624014778416469559352415235942001479492660343437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1213182605 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_perf.1213182605 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_perf.1213182605 -covoverwrite' seed=112641230111156602525400529379624014778416469559352415235942001479492660343437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112641230111156602525400529379624014778416469559352415235942001479492660343437 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 24421689791390729906462678287354319893616496374751182775722899945478487829459 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2665769939 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_long_xfer_wo_dly.2665769939 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_long_xfer_wo_dly.2665769939 -covoverwrite' seed=24421689791390729906462678287354319893616496374751182775722899945478487829459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24421689791390729906462678287354319893616496374751182775722899945478487829459 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 85203168970150118308990242582839556369737766508019149167355551532318852010647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=308171415 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_stress_all_with_rand_reset.308171415 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_stress_all_with_rand_reset.308171415 -covoverwrite' seed=85203168970150118308990242582839556369737766508019149167355551532318852010647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85203168970150118308990242582839556369737766508019149167355551532318852010647 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 31862080740301622589908805354922726080199468358722630538883186112173217566116 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1429097892 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_stress_all.1429097892 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_stress_all.1429097892 -covoverwrite' seed=31862080740301622589908805354922726080199468358722630538883186112173217566116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31862080740301622589908805354922726080199468358722630538883186112173217566116 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 91975733614821719380571056756828413587861424882464586614666296014958941284196 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1674422116 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/6.uart_tl_errors.1674422116 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.uart_tl_errors.1674422116 -covoverwrite' seed=91975733614821719380571056756828413587861424882464586614666296014958941284196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91975733614821719380571056756828413587861424882464586614666296014958941284196 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 7330537966226169335346512164236761769808104139355610417271183408524469198672 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3175079760 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/6.uart_tl_intg_err.3175079760 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.uart_tl_intg_err.3175079760 -covoverwrite' seed=7330537966226169335346512164236761769808104139355610417271183408524469198672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7330537966226169335346512164236761769808104139355610417271183408524469198672 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 42415087419481277191912312618991431859777328474400669400808275180836850914022 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1209946854 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/6.uart_intr_test.1209946854 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.uart_intr_test.1209946854 -covoverwrite' seed=42415087419481277191912312618991431859777328474400669400808275180836850914022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42415087419481277191912312618991431859777328474400669400808275180836850914022 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 73429972091865487741798845476362978315624941982652053704174065360588630212260 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2660581028 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/6.uart_alert_test.2660581028 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 6.uart_alert_test.2660581028 -covoverwrite' seed=73429972091865487741798845476362978315624941982652053704174065360588630212260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73429972091865487741798845476362978315624941982652053704174065360588630212260 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/6.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 52569382395804447949028974974283525675915839181295810572477152466516333032202 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1996485386 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_smoke.1996485386 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_smoke.1996485386 -covoverwrite' seed=52569382395804447949028974974283525675915839181295810572477152466516333032202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52569382395804447949028974974283525675915839181295810572477152466516333032202 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 99624875801484876892331412520466749397749904701498071537394176916080701476318 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3318484446 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_tx_rx.3318484446 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_tx_rx.3318484446 -covoverwrite' seed=99624875801484876892331412520466749397749904701498071537394176916080701476318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99624875801484876892331412520466749397749904701498071537394176916080701476318 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 20634396923321238505646178069026758494890854849185588000797249747416753557208 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2709442264 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_fifo_full.2709442264 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_fifo_full.2709442264 -covoverwrite' seed=20634396923321238505646178069026758494890854849185588000797249747416753557208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20634396923321238505646178069026758494890854849185588000797249747416753557208 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 57563233866865249658770456808943138700076397939027927763268287904695561193858 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2393344386 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_fifo_overflow.2393344386 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_fifo_overflow.2393344386 -covoverwrite' seed=57563233866865249658770456808943138700076397939027927763268287904695561193858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57563233866865249658770456808943138700076397939027927763268287904695561193858 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 3581820956684231061957571321048449894604551924243917772489334228183828092282 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=813913466 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_fifo_reset.813913466 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_fifo_reset.813913466 -covoverwrite' seed=3581820956684231061957571321048449894604551924243917772489334228183828092282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3581820956684231061957571321048449894604551924243917772489334228183828092282 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 69206237517455367299744324483353337998937551669932174256999874164866320868400 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2708120624 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_rx_oversample.2708120624 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_rx_oversample.2708120624 -covoverwrite' seed=69206237517455367299744324483353337998937551669932174256999874164866320868400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69206237517455367299744324483353337998937551669932174256999874164866320868400 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 62823885237329561148053113619626069471554156568959044916792368660377935672104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1266545448 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_intr.1266545448 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_intr.1266545448 -covoverwrite' seed=62823885237329561148053113619626069471554156568959044916792368660377935672104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62823885237329561148053113619626069471554156568959044916792368660377935672104 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 6826097332372367339928522287431625046002027858773609918050502688366970092731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=373374139 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_noise_filter.373374139 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_noise_filter.373374139 -covoverwrite' seed=6826097332372367339928522287431625046002027858773609918050502688366970092731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6826097332372367339928522287431625046002027858773609918050502688366970092731 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 83234369853951387162822111896468496714883313541772864786066010149634512530164 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3737135860 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_rx_start_bit_filter.3737135860 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_rx_start_bit_filter.3737135860 -covoverwrite' seed=83234369853951387162822111896468496714883313541772864786066010149634512530164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83234369853951387162822111896468496714883313541772864786066010149634512530164 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 108604941535648844482944932517715329123587211845466263853546942363548730382453 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1623316597 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_rx_parity_err.1623316597 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_rx_parity_err.1623316597 -covoverwrite' seed=108604941535648844482944932517715329123587211845466263853546942363548730382453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108604941535648844482944932517715329123587211845466263853546942363548730382453 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 61392869129661647686852367865946893740164542463749165048130029876284278161064 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2338569896 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_tx_ovrd.2338569896 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_tx_ovrd.2338569896 -covoverwrite' seed=61392869129661647686852367865946893740164542463749165048130029876284278161064 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61392869129661647686852367865946893740164542463749165048130029876284278161064 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 29364123627835758976095027378762398657220545489388671787491325534574723376211 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3794445395 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_loopback.3794445395 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_loopback.3794445395 -covoverwrite' seed=29364123627835758976095027378762398657220545489388671787491325534574723376211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29364123627835758976095027378762398657220545489388671787491325534574723376211 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 47852218890588486317114550296180675595259294120608991840765963437905556447882 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2645205642 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_perf.2645205642 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_perf.2645205642 -covoverwrite' seed=47852218890588486317114550296180675595259294120608991840765963437905556447882 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47852218890588486317114550296180675595259294120608991840765963437905556447882 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 77651562043465408014327610706296301687332647384348477192066801792002800298216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2473666792 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_long_xfer_wo_dly.2473666792 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_long_xfer_wo_dly.2473666792 -covoverwrite' seed=77651562043465408014327610706296301687332647384348477192066801792002800298216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77651562043465408014327610706296301687332647384348477192066801792002800298216 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 51801967388457955643014069517168158356263886691629808870177948643302024421990 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3684442726 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_stress_all_with_rand_reset.3684442726 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_stress_all_with_rand_reset.3684442726 -covoverwrite' seed=51801967388457955643014069517168158356263886691629808870177948643302024421990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51801967388457955643014069517168158356263886691629808870177948643302024421990 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 88911767594496616414111167304602006386554484963450293835930160935513886080516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1528086020 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_stress_all.1528086020 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_stress_all.1528086020 -covoverwrite' seed=88911767594496616414111167304602006386554484963450293835930160935513886080516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88911767594496616414111167304602006386554484963450293835930160935513886080516 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 48311659595609013417529072354728759558910583662234979357253484070368023366955 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2185710891 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/7.uart_tl_errors.2185710891 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.uart_tl_errors.2185710891 -covoverwrite' seed=48311659595609013417529072354728759558910583662234979357253484070368023366955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48311659595609013417529072354728759558910583662234979357253484070368023366955 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 10789507013634638143719454181888594727635668773522572413955611884417144431045 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1437180357 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/7.uart_tl_intg_err.1437180357 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.uart_tl_intg_err.1437180357 -covoverwrite' seed=10789507013634638143719454181888594727635668773522572413955611884417144431045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10789507013634638143719454181888594727635668773522572413955611884417144431045 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 103127271414496097049345558901090312954396868080020796244413130066667530026139 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3826449563 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/7.uart_intr_test.3826449563 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.uart_intr_test.3826449563 -covoverwrite' seed=103127271414496097049345558901090312954396868080020796244413130066667530026139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103127271414496097049345558901090312954396868080020796244413130066667530026139 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 90888869371430202182442129302197149539813105710976265698455166325139799801220 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2264399236 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/7.uart_alert_test.2264399236 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 7.uart_alert_test.2264399236 -covoverwrite' seed=90888869371430202182442129302197149539813105710976265698455166325139799801220 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90888869371430202182442129302197149539813105710976265698455166325139799801220 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/7.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 33430128776064292966096377083534206259913853854554852617124561737017770371918 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1903422286 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_smoke.1903422286 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_smoke.1903422286 -covoverwrite' seed=33430128776064292966096377083534206259913853854554852617124561737017770371918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33430128776064292966096377083534206259913853854554852617124561737017770371918 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 109938764626498211656848749579167627020672138620076308296753036026547156519479 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2212727351 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_tx_rx.2212727351 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_tx_rx.2212727351 -covoverwrite' seed=109938764626498211656848749579167627020672138620076308296753036026547156519479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109938764626498211656848749579167627020672138620076308296753036026547156519479 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 70010154672578600981926370592915864559164871081953894484034657739223428887262 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=119141086 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_fifo_full.119141086 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_fifo_full.119141086 -covoverwrite' seed=70010154672578600981926370592915864559164871081953894484034657739223428887262 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70010154672578600981926370592915864559164871081953894484034657739223428887262 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 57412303319563392220724859742434956115656887300129120851015338767788206862027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1780887243 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_fifo_overflow.1780887243 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_fifo_overflow.1780887243 -covoverwrite' seed=57412303319563392220724859742434956115656887300129120851015338767788206862027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57412303319563392220724859742434956115656887300129120851015338767788206862027 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 76250269818030978167524185885868338008516698659767242828306539936123372121666 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1342647874 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_fifo_reset.1342647874 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_fifo_reset.1342647874 -covoverwrite' seed=76250269818030978167524185885868338008516698659767242828306539936123372121666 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76250269818030978167524185885868338008516698659767242828306539936123372121666 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 77611541114373594672055165135598835354606898616722833063017412134691691941969 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2716717137 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_rx_oversample.2716717137 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_rx_oversample.2716717137 -covoverwrite' seed=77611541114373594672055165135598835354606898616722833063017412134691691941969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77611541114373594672055165135598835354606898616722833063017412134691691941969 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 45983721969115316627567289472246581997716423256188812770221523352325070890047 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3738018879 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_intr.3738018879 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_intr.3738018879 -covoverwrite' seed=45983721969115316627567289472246581997716423256188812770221523352325070890047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45983721969115316627567289472246581997716423256188812770221523352325070890047 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 99683687679535664211754301023534827202727426566876387450304827278605800189987 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=603992099 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_noise_filter.603992099 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_noise_filter.603992099 -covoverwrite' seed=99683687679535664211754301023534827202727426566876387450304827278605800189987 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99683687679535664211754301023534827202727426566876387450304827278605800189987 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 36023999512722745991882414849321383978241049954350915910111459485405948889982 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3844819838 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_rx_start_bit_filter.3844819838 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_rx_start_bit_filter.3844819838 -covoverwrite' seed=36023999512722745991882414849321383978241049954350915910111459485405948889982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36023999512722745991882414849321383978241049954350915910111459485405948889982 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 101422147695195747877251408400824008665236111538302223493556992007248939428688 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4260735824 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_rx_parity_err.4260735824 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_rx_parity_err.4260735824 -covoverwrite' seed=101422147695195747877251408400824008665236111538302223493556992007248939428688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101422147695195747877251408400824008665236111538302223493556992007248939428688 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 63333454167927425949146558019091053053910578148442973753086664171375836758204 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2079555772 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_tx_ovrd.2079555772 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_tx_ovrd.2079555772 -covoverwrite' seed=63333454167927425949146558019091053053910578148442973753086664171375836758204 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63333454167927425949146558019091053053910578148442973753086664171375836758204 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 74984142135661703879767372626823479713271513054010442256275282379289029405634 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2566024130 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_loopback.2566024130 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_loopback.2566024130 -covoverwrite' seed=74984142135661703879767372626823479713271513054010442256275282379289029405634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74984142135661703879767372626823479713271513054010442256275282379289029405634 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 48579925276029799523893449035616111960039735774632015799415150926434019870183 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2792654311 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_perf.2792654311 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_perf.2792654311 -covoverwrite' seed=48579925276029799523893449035616111960039735774632015799415150926434019870183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48579925276029799523893449035616111960039735774632015799415150926434019870183 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 43127916346488227576035788782966289279306447277556772634098877264026258815301 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4092246341 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_long_xfer_wo_dly.4092246341 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_long_xfer_wo_dly.4092246341 -covoverwrite' seed=43127916346488227576035788782966289279306447277556772634098877264026258815301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43127916346488227576035788782966289279306447277556772634098877264026258815301 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 71611056242253860837353129841290560344493672503476471226517885005130595897584 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=516231408 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_stress_all_with_rand_reset.516231408 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_stress_all_with_rand_reset.516231408 -covoverwrite' seed=71611056242253860837353129841290560344493672503476471226517885005130595897584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71611056242253860837353129841290560344493672503476471226517885005130595897584 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 19458432201719310889417774316909638136996812901249613234061005440715789362543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=705095023 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_stress_all.705095023 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_stress_all.705095023 -covoverwrite' seed=19458432201719310889417774316909638136996812901249613234061005440715789362543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19458432201719310889417774316909638136996812901249613234061005440715789362543 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 67534875420028238139414608596442706836011022517933341377674304875774259267645 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2369816637 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/8.uart_tl_errors.2369816637 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.uart_tl_errors.2369816637 -covoverwrite' seed=67534875420028238139414608596442706836011022517933341377674304875774259267645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67534875420028238139414608596442706836011022517933341377674304875774259267645 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 47141654271473672030886957154231198586710667793309168127172509149743930600337 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1896278929 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/8.uart_tl_intg_err.1896278929 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.uart_tl_intg_err.1896278929 -covoverwrite' seed=47141654271473672030886957154231198586710667793309168127172509149743930600337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47141654271473672030886957154231198586710667793309168127172509149743930600337 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 35801572610816938261700380265606519570448671394456573859267110132315710560954 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2841909946 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/8.uart_intr_test.2841909946 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.uart_intr_test.2841909946 -covoverwrite' seed=35801572610816938261700380265606519570448671394456573859267110132315710560954 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35801572610816938261700380265606519570448671394456573859267110132315710560954 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 96050509860778215643705553447057766924414083014623566555947587983066722523120 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3418150896 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/8.uart_alert_test.3418150896 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 8.uart_alert_test.3418150896 -covoverwrite' seed=96050509860778215643705553447057766924414083014623566555947587983066722523120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96050509860778215643705553447057766924414083014623566555947587983066722523120 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/8.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_smoke 69669382861835809965249204328668250847292436243216022908226148969278329537740 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2970567884 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_smoke.2970567884 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_smoke.2970567884 -covoverwrite' seed=69669382861835809965249204328668250847292436243216022908226148969278329537740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69669382861835809965249204328668250847292436243216022908226148969278329537740 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_rx 58576399607144912531720877886487505576421520526116586236570484305619300482046 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_tx_rx/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=726236158 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_tx_rx.726236158 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_tx_rx.726236158 -covoverwrite' seed=58576399607144912531720877886487505576421520526116586236570484305619300482046 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58576399607144912531720877886487505576421520526116586236570484305619300482046 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_tx_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_full 63769889593816958568415394058241171177236968992014687882012986657381088185692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3048688988 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_fifo_full.3048688988 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_fifo_full.3048688988 -covoverwrite' seed=63769889593816958568415394058241171177236968992014687882012986657381088185692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63769889593816958568415394058241171177236968992014687882012986657381088185692 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_overflow 76927530107822493267455076632561496609327389627558499655193371564246290545421 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2955295501 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_fifo_overflow.2955295501 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_fifo_overflow.2955295501 -covoverwrite' seed=76927530107822493267455076632561496609327389627558499655193371564246290545421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76927530107822493267455076632561496609327389627558499655193371564246290545421 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 24358962026714137815910669402880963254881032511788438255533794443593529078656 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3572937600 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_fifo_reset.3572937600 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_fifo_reset.3572937600 -covoverwrite' seed=24358962026714137815910669402880963254881032511788438255533794443593529078656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24358962026714137815910669402880963254881032511788438255533794443593529078656 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_oversample 36828863058320946857401518383083646330815968760020876967129531076345895748668 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_rx_oversample/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3313402940 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_oversample_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_rx_oversample.3313402940 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_rx_oversample.3313402940 -covoverwrite' seed=36828863058320946857401518383083646330815968760020876967129531076345895748668 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36828863058320946857401518383083646330815968760020876967129531076345895748668 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_rx_oversample/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_oversample_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr 88999491414966071296875942485405880950523655630024906310735673992204105104584 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_intr/latest run_opts='+test_timeout_ns=3000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3941416136 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_intr.3941416136 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_intr.3941416136 -covoverwrite' seed=88999491414966071296875942485405880950523655630024906310735673992204105104584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88999491414966071296875942485405880950523655630024906310735673992204105104584 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_noise_filter 108433798136256762896678248579235321271981758997942143648015504251805176112676 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_noise_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2411406884 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_noise_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_noise_filter.2411406884 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_noise_filter.2411406884 -covoverwrite' seed=108433798136256762896678248579235321271981758997942143648015504251805176112676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108433798136256762896678248579235321271981758997942143648015504251805176112676 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_noise_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_noise_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_start_bit_filter 103802909100885725846463972811047367380649078877842859678133838725857699933948 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_rx_start_bit_filter/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1775742716 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_start_bit_filter_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_rx_start_bit_filter.1775742716 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_rx_start_bit_filter.1775742716 -covoverwrite' seed=103802909100885725846463972811047367380649078877842859678133838725857699933948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103802909100885725846463972811047367380649078877842859678133838725857699933948 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_rx_start_bit_filter/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_start_bit_filter_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_rx_parity_err 45563526559563679961037803388909317929010374816521298598665214246010340162280 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_rx_parity_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3949116136 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_rx_parity_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_rx_parity_err.3949116136 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_rx_parity_err.3949116136 -covoverwrite' seed=45563526559563679961037803388909317929010374816521298598665214246010340162280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45563526559563679961037803388909317929010374816521298598665214246010340162280 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_rx_parity_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_rx_parity_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tx_ovrd 41601788231319224616469948735427201720108396589514935212505738897818763289323 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_tx_ovrd/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1685480171 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_tx_ovrd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_tx_ovrd.1685480171 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_tx_ovrd.1685480171 -covoverwrite' seed=41601788231319224616469948735427201720108396589514935212505738897818763289323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41601788231319224616469948735427201720108396589514935212505738897818763289323 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_tx_ovrd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_tx_ovrd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_loopback 4765243768895228806343000072095854497381095581348673157787093649855804317044 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_loopback/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=906468724 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_loopback_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_loopback.906468724 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_loopback.906468724 -covoverwrite' seed=4765243768895228806343000072095854497381095581348673157787093649855804317044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4765243768895228806343000072095854497381095581348673157787093649855804317044 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_loopback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_loopback_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_perf 19415546296115213742956647701860285640304330932468208426591657261917413152306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_perf/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=501847602 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_perf.501847602 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_perf.501847602 -covoverwrite' seed=19415546296115213742956647701860285640304330932468208426591657261917413152306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19415546296115213742956647701860285640304330932468208426591657261917413152306 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_long_xfer_wo_dly 30953959036453050274157269607545385158047771953730199130390739569323834261137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_long_xfer_wo_dly/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3095576209 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_long_xfer_wo_dly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_long_xfer_wo_dly.3095576209 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_long_xfer_wo_dly.3095576209 -covoverwrite' seed=30953959036453050274157269607545385158047771953730199130390739569323834261137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30953959036453050274157269607545385158047771953730199130390739569323834261137 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_long_xfer_wo_dly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_long_xfer_wo_dly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 47187018723406760898562483358147915466415988424302284091707729398331196015133 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2797568541 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_stress_all_with_rand_reset.2797568541 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_stress_all_with_rand_reset.2797568541 -covoverwrite' seed=47187018723406760898562483358147915466415988424302284091707729398331196015133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47187018723406760898562483358147915466415988424302284091707729398331196015133 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all 84930310264728308587132192121251417359074869713916729609453222175962923654390 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_stress_all/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=457563382 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_stress_all.457563382 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_stress_all.457563382 -covoverwrite' seed=84930310264728308587132192121251417359074869713916729609453222175962923654390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84930310264728308587132192121251417359074869713916729609453222175962923654390 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 72249820385242158901669199495017434435831782808038157530514221182646140661517 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=146403085 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/9.uart_tl_errors.146403085 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.uart_tl_errors.146403085 -covoverwrite' seed=72249820385242158901669199495017434435831782808038157530514221182646140661517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72249820385242158901669199495017434435831782808038157530514221182646140661517 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 37473573598120099692214609341785409467529678340481879828074395240974483631588 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2754522596 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/9.uart_tl_intg_err.2754522596 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.uart_tl_intg_err.2754522596 -covoverwrite' seed=37473573598120099692214609341785409467529678340481879828074395240974483631588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37473573598120099692214609341785409467529678340481879828074395240974483631588 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_intr_test 98882143851828139952357206985704978058408585573403218327549743676387999546989 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=6487661 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/9.uart_intr_test.6487661 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.uart_intr_test.6487661 -covoverwrite' seed=98882143851828139952357206985704978058408585573403218327549743676387999546989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98882143851828139952357206985704978058408585573403218327549743676387999546989 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_alert_test 17008716806948589720346310280920521911722090961382978287012949020978328616868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=700170148 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/9.uart_alert_test.700170148 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 9.uart_alert_test.700170148 -covoverwrite' seed=17008716806948589720346310280920521911722090961382978287012949020978328616868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17008716806948589720346310280920521911722090961382978287012949020978328616868 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/9.uart_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 17809282055931746917669347941338438161608240090787522273699266575771030182013 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3534149757 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/10.uart_fifo_reset.3534149757 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 10.uart_fifo_reset.3534149757 -covoverwrite' seed=17809282055931746917669347941338438161608240090787522273699266575771030182013 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17809282055931746917669347941338438161608240090787522273699266575771030182013 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 115470172759151369846338657977269024280341466081788922405601523596298452821987 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2514577379 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/10.uart_stress_all_with_rand_reset.2514577379 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 10.uart_stress_all_with_rand_reset.2514577379 -covoverwrite' seed=115470172759151369846338657977269024280341466081788922405601523596298452821987 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115470172759151369846338657977269024280341466081788922405601523596298452821987 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 100136166055347324937195051374932586001323206397711267662161659735205755647221 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=327578869 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/10.uart_tl_errors.327578869 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.uart_tl_errors.327578869 -covoverwrite' seed=100136166055347324937195051374932586001323206397711267662161659735205755647221 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100136166055347324937195051374932586001323206397711267662161659735205755647221 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 91578237401498500853910407188345237287801703114869508734846631148855442596636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1078256412 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/10.uart_tl_intg_err.1078256412 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.uart_tl_intg_err.1078256412 -covoverwrite' seed=91578237401498500853910407188345237287801703114869508734846631148855442596636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91578237401498500853910407188345237287801703114869508734846631148855442596636 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/10.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 139093304084978522683804380280041256318728842719869295518484718483589919327 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1646883423 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/11.uart_fifo_reset.1646883423 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 11.uart_fifo_reset.1646883423 -covoverwrite' seed=139093304084978522683804380280041256318728842719869295518484718483589919327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=139093304084978522683804380280041256318728842719869295518484718483589919327 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 65219372066699045089186677912906715594636820839302807117806853021573166762074 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2840692826 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/11.uart_stress_all_with_rand_reset.2840692826 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 11.uart_stress_all_with_rand_reset.2840692826 -covoverwrite' seed=65219372066699045089186677912906715594636820839302807117806853021573166762074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65219372066699045089186677912906715594636820839302807117806853021573166762074 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 94866081331582376330989067345561945790685911108743780970427724078267779614305 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3332474465 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/11.uart_tl_errors.3332474465 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.uart_tl_errors.3332474465 -covoverwrite' seed=94866081331582376330989067345561945790685911108743780970427724078267779614305 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94866081331582376330989067345561945790685911108743780970427724078267779614305 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 115627533907452187781108255486083895893411136159220621540277273877847101603152 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3523935568 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/11.uart_tl_intg_err.3523935568 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.uart_tl_intg_err.3523935568 -covoverwrite' seed=115627533907452187781108255486083895893411136159220621540277273877847101603152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115627533907452187781108255486083895893411136159220621540277273877847101603152 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/11.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 98826514241602439419495638650658771135846745203593328148700344831435830616364 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=33710380 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/12.uart_fifo_reset.33710380 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 12.uart_fifo_reset.33710380 -covoverwrite' seed=98826514241602439419495638650658771135846745203593328148700344831435830616364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98826514241602439419495638650658771135846745203593328148700344831435830616364 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 12667000164230523557875635401069192705565470760126468610216518398042016959746 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=72207618 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/12.uart_stress_all_with_rand_reset.72207618 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 12.uart_stress_all_with_rand_reset.72207618 -covoverwrite' seed=12667000164230523557875635401069192705565470760126468610216518398042016959746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12667000164230523557875635401069192705565470760126468610216518398042016959746 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 15833696295880110881036120971035437915256795528392056413812794226401024823935 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3114422911 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/12.uart_tl_errors.3114422911 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.uart_tl_errors.3114422911 -covoverwrite' seed=15833696295880110881036120971035437915256795528392056413812794226401024823935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15833696295880110881036120971035437915256795528392056413812794226401024823935 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 48943515703383708788074939141580029335211239339122705780973955500826487536657 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2834676753 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/12.uart_tl_intg_err.2834676753 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.uart_tl_intg_err.2834676753 -covoverwrite' seed=48943515703383708788074939141580029335211239339122705780973955500826487536657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48943515703383708788074939141580029335211239339122705780973955500826487536657 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/12.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 20702472156790798032825979397776996212453941999659492046317533345985509904187 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3292974907 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/13.uart_fifo_reset.3292974907 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 13.uart_fifo_reset.3292974907 -covoverwrite' seed=20702472156790798032825979397776996212453941999659492046317533345985509904187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20702472156790798032825979397776996212453941999659492046317533345985509904187 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 20834471843413015604023082977752808541214479354306684186702261729859392893877 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1622274997 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/13.uart_stress_all_with_rand_reset.1622274997 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 13.uart_stress_all_with_rand_reset.1622274997 -covoverwrite' seed=20834471843413015604023082977752808541214479354306684186702261729859392893877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20834471843413015604023082977752808541214479354306684186702261729859392893877 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 55691851416076152334040571112661631720489660645660374392220177783190859301812 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=388252596 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/13.uart_tl_errors.388252596 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.uart_tl_errors.388252596 -covoverwrite' seed=55691851416076152334040571112661631720489660645660374392220177783190859301812 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55691851416076152334040571112661631720489660645660374392220177783190859301812 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 7171045436938424222897135579138986780076059278659027343693095995620811491922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1267354194 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/13.uart_tl_intg_err.1267354194 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.uart_tl_intg_err.1267354194 -covoverwrite' seed=7171045436938424222897135579138986780076059278659027343693095995620811491922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7171045436938424222897135579138986780076059278659027343693095995620811491922 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/13.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 73649030443517315899395695968699776241290025734426389740512109425366199222350 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4114137166 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/14.uart_fifo_reset.4114137166 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 14.uart_fifo_reset.4114137166 -covoverwrite' seed=73649030443517315899395695968699776241290025734426389740512109425366199222350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73649030443517315899395695968699776241290025734426389740512109425366199222350 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 92730303870666873975677915101057310447665939345635117346455571448852998232450 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4131363202 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/14.uart_stress_all_with_rand_reset.4131363202 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 14.uart_stress_all_with_rand_reset.4131363202 -covoverwrite' seed=92730303870666873975677915101057310447665939345635117346455571448852998232450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92730303870666873975677915101057310447665939345635117346455571448852998232450 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 66553741589572208745433252324798195591290435139161533604616546975550785835059 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1955188787 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/14.uart_tl_errors.1955188787 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.uart_tl_errors.1955188787 -covoverwrite' seed=66553741589572208745433252324798195591290435139161533604616546975550785835059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66553741589572208745433252324798195591290435139161533604616546975550785835059 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 80193961927746215390675669056719469727015596778968623069522341911392368741688 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1892961592 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/14.uart_tl_intg_err.1892961592 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.uart_tl_intg_err.1892961592 -covoverwrite' seed=80193961927746215390675669056719469727015596778968623069522341911392368741688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80193961927746215390675669056719469727015596778968623069522341911392368741688 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/14.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 112590687049590229172481491523047096736912804422396151621112201483836022170579 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3606422483 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/15.uart_fifo_reset.3606422483 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 15.uart_fifo_reset.3606422483 -covoverwrite' seed=112590687049590229172481491523047096736912804422396151621112201483836022170579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112590687049590229172481491523047096736912804422396151621112201483836022170579 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 74210575829006521779240606399523863156180223454606601860985856724187343822385 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2472615473 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/15.uart_stress_all_with_rand_reset.2472615473 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 15.uart_stress_all_with_rand_reset.2472615473 -covoverwrite' seed=74210575829006521779240606399523863156180223454606601860985856724187343822385 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74210575829006521779240606399523863156180223454606601860985856724187343822385 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 10053893272677693691251517675296289256156351803198828545012348333163803888498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1934936946 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/15.uart_tl_errors.1934936946 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.uart_tl_errors.1934936946 -covoverwrite' seed=10053893272677693691251517675296289256156351803198828545012348333163803888498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10053893272677693691251517675296289256156351803198828545012348333163803888498 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 70711029668856047375764113267089910750915557533646627848499391921072948227543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1778232791 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/15.uart_tl_intg_err.1778232791 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.uart_tl_intg_err.1778232791 -covoverwrite' seed=70711029668856047375764113267089910750915557533646627848499391921072948227543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70711029668856047375764113267089910750915557533646627848499391921072948227543 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/15.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 86007452138588234677473964681847405067085676238650266004090765075309828111371 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=39975947 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/16.uart_fifo_reset.39975947 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 16.uart_fifo_reset.39975947 -covoverwrite' seed=86007452138588234677473964681847405067085676238650266004090765075309828111371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86007452138588234677473964681847405067085676238650266004090765075309828111371 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 29968997716232274246661021279715611394486307151641422969396198812513522935411 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=633333363 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/16.uart_stress_all_with_rand_reset.633333363 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 16.uart_stress_all_with_rand_reset.633333363 -covoverwrite' seed=29968997716232274246661021279715611394486307151641422969396198812513522935411 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29968997716232274246661021279715611394486307151641422969396198812513522935411 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 101097146401016140067513819139931159412179468103175656635123065428256309372624 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2474895056 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/16.uart_tl_errors.2474895056 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.uart_tl_errors.2474895056 -covoverwrite' seed=101097146401016140067513819139931159412179468103175656635123065428256309372624 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101097146401016140067513819139931159412179468103175656635123065428256309372624 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 22970101493100977160573177935047400384358840090686932175555652190018469371704 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=840441656 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/16.uart_tl_intg_err.840441656 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.uart_tl_intg_err.840441656 -covoverwrite' seed=22970101493100977160573177935047400384358840090686932175555652190018469371704 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22970101493100977160573177935047400384358840090686932175555652190018469371704 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/16.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 115339787571708877451102366596009804149040858067772086916856180148223307007860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2315372404 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/17.uart_fifo_reset.2315372404 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 17.uart_fifo_reset.2315372404 -covoverwrite' seed=115339787571708877451102366596009804149040858067772086916856180148223307007860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115339787571708877451102366596009804149040858067772086916856180148223307007860 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 7651934411919343674706513249665954760620924120375946638685429032727761229623 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2861406007 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/17.uart_stress_all_with_rand_reset.2861406007 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 17.uart_stress_all_with_rand_reset.2861406007 -covoverwrite' seed=7651934411919343674706513249665954760620924120375946638685429032727761229623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7651934411919343674706513249665954760620924120375946638685429032727761229623 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 6406166482602699441897002957278833133955207698996737014355956523741356987168 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1278972704 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/17.uart_tl_errors.1278972704 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.uart_tl_errors.1278972704 -covoverwrite' seed=6406166482602699441897002957278833133955207698996737014355956523741356987168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6406166482602699441897002957278833133955207698996737014355956523741356987168 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 34038293616137815320184736254614071247307945500592481383816392347378842549450 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1637301450 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/17.uart_tl_intg_err.1637301450 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.uart_tl_intg_err.1637301450 -covoverwrite' seed=34038293616137815320184736254614071247307945500592481383816392347378842549450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34038293616137815320184736254614071247307945500592481383816392347378842549450 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/17.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 15607867643366440479909340236972259069122620568232531923213012899392547746456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=45380248 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/18.uart_fifo_reset.45380248 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 18.uart_fifo_reset.45380248 -covoverwrite' seed=15607867643366440479909340236972259069122620568232531923213012899392547746456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15607867643366440479909340236972259069122620568232531923213012899392547746456 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 1240245601266955312884261526746575858039061461206177668161188981835510078678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3606600918 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/18.uart_stress_all_with_rand_reset.3606600918 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 18.uart_stress_all_with_rand_reset.3606600918 -covoverwrite' seed=1240245601266955312884261526746575858039061461206177668161188981835510078678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1240245601266955312884261526746575858039061461206177668161188981835510078678 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 33201796034423372623742244267437777336005497696241194706852157323886839234536 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1305247720 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/18.uart_tl_errors.1305247720 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.uart_tl_errors.1305247720 -covoverwrite' seed=33201796034423372623742244267437777336005497696241194706852157323886839234536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33201796034423372623742244267437777336005497696241194706852157323886839234536 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 115039972935990345623025608576012121223604563237583347012359180983885512550294 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2378672022 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/18.uart_tl_intg_err.2378672022 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.uart_tl_intg_err.2378672022 -covoverwrite' seed=115039972935990345623025608576012121223604563237583347012359180983885512550294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115039972935990345623025608576012121223604563237583347012359180983885512550294 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/18.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 110787441202110385818800196376189412897671526733174298175550582184687221025177 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/19.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2645764505 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/19.uart_fifo_reset.2645764505 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 19.uart_fifo_reset.2645764505 -covoverwrite' seed=110787441202110385818800196376189412897671526733174298175550582184687221025177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110787441202110385818800196376189412897671526733174298175550582184687221025177 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/19.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_stress_all_with_rand_reset 46649891786786652857360584639584773064876577844094001900604871872067904047571 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/19.uart_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=uart_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=745638355 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/19.uart_stress_all_with_rand_reset.745638355 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 19.uart_stress_all_with_rand_reset.745638355 -covoverwrite' seed=46649891786786652857360584639584773064876577844094001900604871872067904047571 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46649891786786652857360584639584773064876577844094001900604871872067904047571 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/19.uart_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 114480518986569076575044929402963510219788392926171407547779813256263546961817 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/19.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3359637401 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/19.uart_tl_errors.3359637401 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.uart_tl_errors.3359637401 -covoverwrite' seed=114480518986569076575044929402963510219788392926171407547779813256263546961817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114480518986569076575044929402963510219788392926171407547779813256263546961817 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/19.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 92018537989745714012870524894468461068457042978409918999923609064616183910680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/19.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1657983256 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/19.uart_tl_intg_err.1657983256 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.uart_tl_intg_err.1657983256 -covoverwrite' seed=92018537989745714012870524894468461068457042978409918999923609064616183910680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92018537989745714012870524894468461068457042978409918999923609064616183910680 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/19.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 71393270698177320906881053211234521951067951697699015807205865720081584258109 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/20.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3459546173 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/20.uart_fifo_reset.3459546173 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 20.uart_fifo_reset.3459546173 -covoverwrite' seed=71393270698177320906881053211234521951067951697699015807205865720081584258109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71393270698177320906881053211234521951067951697699015807205865720081584258109 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/20.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 17514169228711028006126427805891558853237622341572418860108455175126684682706 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/20.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3125955026 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/20.uart_tl_errors.3125955026 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.uart_tl_errors.3125955026 -covoverwrite' seed=17514169228711028006126427805891558853237622341572418860108455175126684682706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17514169228711028006126427805891558853237622341572418860108455175126684682706 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/20.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 97789436748174686411269538594499035514593495325099753702011828096368543738945 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/20.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3018009665 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/20.uart_tl_intg_err.3018009665 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.uart_tl_intg_err.3018009665 -covoverwrite' seed=97789436748174686411269538594499035514593495325099753702011828096368543738945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97789436748174686411269538594499035514593495325099753702011828096368543738945 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/20.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 51005113534091143381057131405245494520589580659345450360979890404874235184001 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2575074177 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/21.uart_fifo_reset.2575074177 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 21.uart_fifo_reset.2575074177 -covoverwrite' seed=51005113534091143381057131405245494520589580659345450360979890404874235184001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51005113534091143381057131405245494520589580659345450360979890404874235184001 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 65874595126674632662695786058693669003286268105026485836625137294263515549343 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1093602975 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/21.uart_tl_errors.1093602975 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.uart_tl_errors.1093602975 -covoverwrite' seed=65874595126674632662695786058693669003286268105026485836625137294263515549343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65874595126674632662695786058693669003286268105026485836625137294263515549343 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 33279116497686406950714424175017677180453183407277209540439262876516790006975 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2047571135 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/21.uart_tl_intg_err.2047571135 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.uart_tl_intg_err.2047571135 -covoverwrite' seed=33279116497686406950714424175017677180453183407277209540439262876516790006975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33279116497686406950714424175017677180453183407277209540439262876516790006975 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/21.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 24083877434033034159729780287630665739710290260815226618917528569542379473157 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/22.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2249361669 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/22.uart_fifo_reset.2249361669 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 22.uart_fifo_reset.2249361669 -covoverwrite' seed=24083877434033034159729780287630665739710290260815226618917528569542379473157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24083877434033034159729780287630665739710290260815226618917528569542379473157 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/22.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 1361319431459713458467031453290279568507463097731115794982459827038085176717 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/22.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3758611853 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/22.uart_tl_errors.3758611853 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.uart_tl_errors.3758611853 -covoverwrite' seed=1361319431459713458467031453290279568507463097731115794982459827038085176717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1361319431459713458467031453290279568507463097731115794982459827038085176717 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/22.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 11940169837652441292045091483151647816898248320412556153517019241524233842430 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/22.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2675519230 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/22.uart_tl_intg_err.2675519230 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.uart_tl_intg_err.2675519230 -covoverwrite' seed=11940169837652441292045091483151647816898248320412556153517019241524233842430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11940169837652441292045091483151647816898248320412556153517019241524233842430 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/22.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 66030308201119450462320783603909923248492750774830886130024633799289241462147 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/23.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=448914819 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/23.uart_fifo_reset.448914819 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 23.uart_fifo_reset.448914819 -covoverwrite' seed=66030308201119450462320783603909923248492750774830886130024633799289241462147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66030308201119450462320783603909923248492750774830886130024633799289241462147 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/23.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 3618132823037883175748741594087909623619104146287771847157552716190523046444 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/23.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=477084204 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/23.uart_tl_errors.477084204 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.uart_tl_errors.477084204 -covoverwrite' seed=3618132823037883175748741594087909623619104146287771847157552716190523046444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3618132823037883175748741594087909623619104146287771847157552716190523046444 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/23.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 44990806209108022167162816887935782521739921294732003007843303216076034894838 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/23.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=904621046 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/23.uart_tl_intg_err.904621046 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.uart_tl_intg_err.904621046 -covoverwrite' seed=44990806209108022167162816887935782521739921294732003007843303216076034894838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44990806209108022167162816887935782521739921294732003007843303216076034894838 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/23.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 69754611410066766434705579222215671807262988944627844896277332866814825390635 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/24.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=308470315 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/24.uart_fifo_reset.308470315 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 24.uart_fifo_reset.308470315 -covoverwrite' seed=69754611410066766434705579222215671807262988944627844896277332866814825390635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69754611410066766434705579222215671807262988944627844896277332866814825390635 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/24.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_errors 10407550053342958179666997722857183557740465025591689569096219230989766847868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/24.uart_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=888106364 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/24.uart_tl_errors.888106364 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.uart_tl_errors.888106364 -covoverwrite' seed=10407550053342958179666997722857183557740465025591689569096219230989766847868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10407550053342958179666997722857183557740465025591689569096219230989766847868 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/24.uart_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_tl_intg_err 17045638106608811510188361787716618401966251435837430495040414990428030377783 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/24.uart_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3438288695 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/cover_reg_top/24.uart_tl_intg_err.3438288695 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.uart_tl_intg_err.3438288695 -covoverwrite' seed=17045638106608811510188361787716618401966251435837430495040414990428030377783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17045638106608811510188361787716618401966251435837430495040414990428030377783 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/24.uart_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 106772229758946276925816258128758070634684958333453960889432938503169591111398 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/25.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=644771558 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/25.uart_fifo_reset.644771558 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 25.uart_fifo_reset.644771558 -covoverwrite' seed=106772229758946276925816258128758070634684958333453960889432938503169591111398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106772229758946276925816258128758070634684958333453960889432938503169591111398 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/25.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 43998592859214401505440597876022957797268445573467235177325250223249243558732 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/26.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3746091852 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/26.uart_fifo_reset.3746091852 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 26.uart_fifo_reset.3746091852 -covoverwrite' seed=43998592859214401505440597876022957797268445573467235177325250223249243558732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43998592859214401505440597876022957797268445573467235177325250223249243558732 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/26.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 15781014357907035088818285580682731419675291434846042934919579867668036729515 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/27.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=533478059 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/27.uart_fifo_reset.533478059 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 27.uart_fifo_reset.533478059 -covoverwrite' seed=15781014357907035088818285580682731419675291434846042934919579867668036729515 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15781014357907035088818285580682731419675291434846042934919579867668036729515 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/27.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 68721678306809251446909703956560058849926935955580908980011164585633277217182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/28.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3362458014 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/28.uart_fifo_reset.3362458014 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 28.uart_fifo_reset.3362458014 -covoverwrite' seed=68721678306809251446909703956560058849926935955580908980011164585633277217182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68721678306809251446909703956560058849926935955580908980011164585633277217182 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/28.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 88822469710715923736355209616279676733726910478278074046662279727282134344487 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/29.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4243743527 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/29.uart_fifo_reset.4243743527 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 29.uart_fifo_reset.4243743527 -covoverwrite' seed=88822469710715923736355209616279676733726910478278074046662279727282134344487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88822469710715923736355209616279676733726910478278074046662279727282134344487 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/29.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 89656326496700218261436026475881431853396219847338381157258767876130146953213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/30.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2295408637 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/30.uart_fifo_reset.2295408637 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 30.uart_fifo_reset.2295408637 -covoverwrite' seed=89656326496700218261436026475881431853396219847338381157258767876130146953213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89656326496700218261436026475881431853396219847338381157258767876130146953213 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/30.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 25731045002807918165499926480119470811896481185645246266211309110877408989137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/31.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1406668753 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/31.uart_fifo_reset.1406668753 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 31.uart_fifo_reset.1406668753 -covoverwrite' seed=25731045002807918165499926480119470811896481185645246266211309110877408989137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25731045002807918165499926480119470811896481185645246266211309110877408989137 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/31.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 91876823112317333199059013042148391568954068224893684233074510757291925466269 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/32.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2117102749 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/32.uart_fifo_reset.2117102749 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 32.uart_fifo_reset.2117102749 -covoverwrite' seed=91876823112317333199059013042148391568954068224893684233074510757291925466269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91876823112317333199059013042148391568954068224893684233074510757291925466269 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/32.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 48783619881723606827007362284518449293853406864676746790373022732063588871785 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/33.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2947411561 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/33.uart_fifo_reset.2947411561 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 33.uart_fifo_reset.2947411561 -covoverwrite' seed=48783619881723606827007362284518449293853406864676746790373022732063588871785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48783619881723606827007362284518449293853406864676746790373022732063588871785 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/33.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 56018182569386971456256258517461395750004999455106425111682392235052309685509 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/34.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1109927173 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/34.uart_fifo_reset.1109927173 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 34.uart_fifo_reset.1109927173 -covoverwrite' seed=56018182569386971456256258517461395750004999455106425111682392235052309685509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56018182569386971456256258517461395750004999455106425111682392235052309685509 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/34.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 58355127984629737386808542912244596149276675606417674836786019966926285461381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/35.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2315802501 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/35.uart_fifo_reset.2315802501 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 35.uart_fifo_reset.2315802501 -covoverwrite' seed=58355127984629737386808542912244596149276675606417674836786019966926285461381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58355127984629737386808542912244596149276675606417674836786019966926285461381 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/35.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 27451077368378568343756441146861033057835744165538021592071840792996717528217 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/36.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3736601753 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/36.uart_fifo_reset.3736601753 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 36.uart_fifo_reset.3736601753 -covoverwrite' seed=27451077368378568343756441146861033057835744165538021592071840792996717528217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27451077368378568343756441146861033057835744165538021592071840792996717528217 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/36.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 80149675352740032723310837454153796468084263664578223333601375027939371619193 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/37.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=570135417 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/37.uart_fifo_reset.570135417 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 37.uart_fifo_reset.570135417 -covoverwrite' seed=80149675352740032723310837454153796468084263664578223333601375027939371619193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80149675352740032723310837454153796468084263664578223333601375027939371619193 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/37.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 77807452919439635738427842864522831578696123460850360944581127671258146429520 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/38.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3251395152 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/38.uart_fifo_reset.3251395152 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 38.uart_fifo_reset.3251395152 -covoverwrite' seed=77807452919439635738427842864522831578696123460850360944581127671258146429520 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77807452919439635738427842864522831578696123460850360944581127671258146429520 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/38.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 32589775287616442311402070796480152565790683950712595741327204324536651450680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/39.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2329774392 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/39.uart_fifo_reset.2329774392 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 39.uart_fifo_reset.2329774392 -covoverwrite' seed=32589775287616442311402070796480152565790683950712595741327204324536651450680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32589775287616442311402070796480152565790683950712595741327204324536651450680 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/39.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 39533018606907846317793543205470837776237758226834748098170146016556562917550 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/40.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4142540974 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/40.uart_fifo_reset.4142540974 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 40.uart_fifo_reset.4142540974 -covoverwrite' seed=39533018606907846317793543205470837776237758226834748098170146016556562917550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39533018606907846317793543205470837776237758226834748098170146016556562917550 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/40.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 98436257885877067792842838082232023540517887606128562788540370532628393011959 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/41.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2860428023 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/41.uart_fifo_reset.2860428023 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 41.uart_fifo_reset.2860428023 -covoverwrite' seed=98436257885877067792842838082232023540517887606128562788540370532628393011959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98436257885877067792842838082232023540517887606128562788540370532628393011959 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/41.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 6506368596600916681179554615011808660534563654789176018748102469284554616079 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/42.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1907633423 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/42.uart_fifo_reset.1907633423 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 42.uart_fifo_reset.1907633423 -covoverwrite' seed=6506368596600916681179554615011808660534563654789176018748102469284554616079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6506368596600916681179554615011808660534563654789176018748102469284554616079 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/42.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 7675882967938601067090922261068648986168789995629801174817870777185973526227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/43.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3227213523 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/43.uart_fifo_reset.3227213523 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 43.uart_fifo_reset.3227213523 -covoverwrite' seed=7675882967938601067090922261068648986168789995629801174817870777185973526227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7675882967938601067090922261068648986168789995629801174817870777185973526227 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/43.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 65204188404773729568478165252745721923005840398728588943497718129386325376843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/44.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1396014923 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/44.uart_fifo_reset.1396014923 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 44.uart_fifo_reset.1396014923 -covoverwrite' seed=65204188404773729568478165252745721923005840398728588943497718129386325376843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65204188404773729568478165252745721923005840398728588943497718129386325376843 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/44.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 103423885001311172647097127690570833557617133131956425414896269373320086951295 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/45.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3447723391 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/45.uart_fifo_reset.3447723391 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 45.uart_fifo_reset.3447723391 -covoverwrite' seed=103423885001311172647097127690570833557617133131956425414896269373320086951295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103423885001311172647097127690570833557617133131956425414896269373320086951295 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/45.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 78033997754966291251387617126764821296554166464886616222461921405493980535755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/46.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=279026635 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/46.uart_fifo_reset.279026635 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 46.uart_fifo_reset.279026635 -covoverwrite' seed=78033997754966291251387617126764821296554166464886616222461921405493980535755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78033997754966291251387617126764821296554166464886616222461921405493980535755 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/46.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 17948855464655452487847920980817674752602405776526682768909695128935292490550 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/47.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1162367798 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/47.uart_fifo_reset.1162367798 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 47.uart_fifo_reset.1162367798 -covoverwrite' seed=17948855464655452487847920980817674752602405776526682768909695128935292490550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17948855464655452487847920980817674752602405776526682768909695128935292490550 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/47.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 106338130595336406955421328285335969473432140726478593585692189527478791360897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/48.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3078148481 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/48.uart_fifo_reset.3078148481 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 48.uart_fifo_reset.3078148481 -covoverwrite' seed=106338130595336406955421328285335969473432140726478593585692189527478791360897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106338130595336406955421328285335969473432140726478593585692189527478791360897 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/48.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 50282793351228039868335994992060344034255854651270611623425748315502700104849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/49.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2243923089 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/49.uart_fifo_reset.2243923089 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 49.uart_fifo_reset.2243923089 -covoverwrite' seed=50282793351228039868335994992060344034255854651270611623425748315502700104849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50282793351228039868335994992060344034255854651270611623425748315502700104849 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/49.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 25989357343440330295921131446904925235094693861376729245151544570198852361185 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/50.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=771218401 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/50.uart_fifo_reset.771218401 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 50.uart_fifo_reset.771218401 -covoverwrite' seed=25989357343440330295921131446904925235094693861376729245151544570198852361185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25989357343440330295921131446904925235094693861376729245151544570198852361185 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/50.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 3930076144937063503212194173336267896080889536601108693325894027878155199730 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/51.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=231777522 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/51.uart_fifo_reset.231777522 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 51.uart_fifo_reset.231777522 -covoverwrite' seed=3930076144937063503212194173336267896080889536601108693325894027878155199730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3930076144937063503212194173336267896080889536601108693325894027878155199730 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/51.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 78147500288878382429590867536267659567188313160954738200141391136904265704180 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/52.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4267811572 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/52.uart_fifo_reset.4267811572 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 52.uart_fifo_reset.4267811572 -covoverwrite' seed=78147500288878382429590867536267659567188313160954738200141391136904265704180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78147500288878382429590867536267659567188313160954738200141391136904265704180 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/52.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 90814270720735017495253566066658882327096513236478772036236735467067396573115 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/53.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=47957947 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/53.uart_fifo_reset.47957947 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 53.uart_fifo_reset.47957947 -covoverwrite' seed=90814270720735017495253566066658882327096513236478772036236735467067396573115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90814270720735017495253566066658882327096513236478772036236735467067396573115 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/53.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 102015100858053371928976613771592592986467426829904732068318203454918978682645 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/54.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2856304405 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/54.uart_fifo_reset.2856304405 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 54.uart_fifo_reset.2856304405 -covoverwrite' seed=102015100858053371928976613771592592986467426829904732068318203454918978682645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102015100858053371928976613771592592986467426829904732068318203454918978682645 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/54.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 42930351307795520362833751474563484968057341718762977709745133767870685724965 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/55.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2730049829 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/55.uart_fifo_reset.2730049829 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 55.uart_fifo_reset.2730049829 -covoverwrite' seed=42930351307795520362833751474563484968057341718762977709745133767870685724965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42930351307795520362833751474563484968057341718762977709745133767870685724965 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/55.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 61073125588196748658678437740630214410295822594352747724884355210808262193866 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/56.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=195621578 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/56.uart_fifo_reset.195621578 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 56.uart_fifo_reset.195621578 -covoverwrite' seed=61073125588196748658678437740630214410295822594352747724884355210808262193866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61073125588196748658678437740630214410295822594352747724884355210808262193866 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/56.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 45440980078168253705728315096941600142632920306418230840942292468290448502556 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/57.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3040325404 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/57.uart_fifo_reset.3040325404 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 57.uart_fifo_reset.3040325404 -covoverwrite' seed=45440980078168253705728315096941600142632920306418230840942292468290448502556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45440980078168253705728315096941600142632920306418230840942292468290448502556 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/57.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 30497009431051574875196825400420585678576383014101730707733452449746883299988 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/58.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=149277332 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/58.uart_fifo_reset.149277332 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 58.uart_fifo_reset.149277332 -covoverwrite' seed=30497009431051574875196825400420585678576383014101730707733452449746883299988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30497009431051574875196825400420585678576383014101730707733452449746883299988 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/58.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 115491470122038911506461126941512343425740684659585800363674026962837027554194 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/59.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=491914130 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/59.uart_fifo_reset.491914130 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 59.uart_fifo_reset.491914130 -covoverwrite' seed=115491470122038911506461126941512343425740684659585800363674026962837027554194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115491470122038911506461126941512343425740684659585800363674026962837027554194 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/59.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 89613191258817385782785798613949541769558662390671234404414383996656881541813 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/60.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2459214517 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/60.uart_fifo_reset.2459214517 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 60.uart_fifo_reset.2459214517 -covoverwrite' seed=89613191258817385782785798613949541769558662390671234404414383996656881541813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89613191258817385782785798613949541769558662390671234404414383996656881541813 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/60.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 63337328198074679056219193289788196612117972967439811710790775776430867863186 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/61.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1549260434 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/61.uart_fifo_reset.1549260434 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 61.uart_fifo_reset.1549260434 -covoverwrite' seed=63337328198074679056219193289788196612117972967439811710790775776430867863186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63337328198074679056219193289788196612117972967439811710790775776430867863186 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/61.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 5052809476691214932252284435927890799048835675248643201591260452107473827281 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/62.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4051088849 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/62.uart_fifo_reset.4051088849 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 62.uart_fifo_reset.4051088849 -covoverwrite' seed=5052809476691214932252284435927890799048835675248643201591260452107473827281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5052809476691214932252284435927890799048835675248643201591260452107473827281 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/62.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 23127455638126494649156232820281081361000019971764048388461908627568088271610 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/63.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2929412858 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/63.uart_fifo_reset.2929412858 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 63.uart_fifo_reset.2929412858 -covoverwrite' seed=23127455638126494649156232820281081361000019971764048388461908627568088271610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23127455638126494649156232820281081361000019971764048388461908627568088271610 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/63.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 17618186640664061870719310713506556023494755868461478404233360108864093149583 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/64.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2973882767 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/64.uart_fifo_reset.2973882767 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 64.uart_fifo_reset.2973882767 -covoverwrite' seed=17618186640664061870719310713506556023494755868461478404233360108864093149583 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17618186640664061870719310713506556023494755868461478404233360108864093149583 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/64.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 26246041867528747408117500214759852877150399363538884740930795091558772522166 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/65.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1213480118 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/65.uart_fifo_reset.1213480118 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 65.uart_fifo_reset.1213480118 -covoverwrite' seed=26246041867528747408117500214759852877150399363538884740930795091558772522166 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26246041867528747408117500214759852877150399363538884740930795091558772522166 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/65.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 48065137756484181611418123926786767662413080560120601098553707680651037404481 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/66.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=79981889 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/66.uart_fifo_reset.79981889 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 66.uart_fifo_reset.79981889 -covoverwrite' seed=48065137756484181611418123926786767662413080560120601098553707680651037404481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48065137756484181611418123926786767662413080560120601098553707680651037404481 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/66.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 1366139599113035005879219301796699022768520756355468122124588197479337497219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/67.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3999339139 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/67.uart_fifo_reset.3999339139 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 67.uart_fifo_reset.3999339139 -covoverwrite' seed=1366139599113035005879219301796699022768520756355468122124588197479337497219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1366139599113035005879219301796699022768520756355468122124588197479337497219 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/67.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 35642126041920841159049088049030934549191338399665977694286246800979284929375 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/68.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1022831455 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/68.uart_fifo_reset.1022831455 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 68.uart_fifo_reset.1022831455 -covoverwrite' seed=35642126041920841159049088049030934549191338399665977694286246800979284929375 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35642126041920841159049088049030934549191338399665977694286246800979284929375 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/68.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 65122651235478782892186364214197821910765839534894408456737303473719517865428 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/69.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=778790356 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/69.uart_fifo_reset.778790356 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 69.uart_fifo_reset.778790356 -covoverwrite' seed=65122651235478782892186364214197821910765839534894408456737303473719517865428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65122651235478782892186364214197821910765839534894408456737303473719517865428 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/69.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 54720620198758295751389086304068388465526256272543383168606785622018599313626 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/70.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2433638618 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/70.uart_fifo_reset.2433638618 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 70.uart_fifo_reset.2433638618 -covoverwrite' seed=54720620198758295751389086304068388465526256272543383168606785622018599313626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54720620198758295751389086304068388465526256272543383168606785622018599313626 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/70.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 92012949177218378260371176151560726674583673887415219582249603537645494321996 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/71.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4215784268 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/71.uart_fifo_reset.4215784268 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 71.uart_fifo_reset.4215784268 -covoverwrite' seed=92012949177218378260371176151560726674583673887415219582249603537645494321996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92012949177218378260371176151560726674583673887415219582249603537645494321996 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/71.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 16924053870056097793299439025453618277007896978304253718253781062242146731733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/72.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2184464085 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/72.uart_fifo_reset.2184464085 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 72.uart_fifo_reset.2184464085 -covoverwrite' seed=16924053870056097793299439025453618277007896978304253718253781062242146731733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16924053870056097793299439025453618277007896978304253718253781062242146731733 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/72.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 27536545872376233370277082741604593011860841826129487562282221073301120732626 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/73.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3439840722 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/73.uart_fifo_reset.3439840722 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 73.uart_fifo_reset.3439840722 -covoverwrite' seed=27536545872376233370277082741604593011860841826129487562282221073301120732626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27536545872376233370277082741604593011860841826129487562282221073301120732626 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/73.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 57107369942422500057279220989501537828601518297563018603442524699150316309428 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/74.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=336956340 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/74.uart_fifo_reset.336956340 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 74.uart_fifo_reset.336956340 -covoverwrite' seed=57107369942422500057279220989501537828601518297563018603442524699150316309428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57107369942422500057279220989501537828601518297563018603442524699150316309428 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/74.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 11285960470401789581310049802376860005212870203172279449626760169999080981298 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/75.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=206144306 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/75.uart_fifo_reset.206144306 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 75.uart_fifo_reset.206144306 -covoverwrite' seed=11285960470401789581310049802376860005212870203172279449626760169999080981298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11285960470401789581310049802376860005212870203172279449626760169999080981298 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/75.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 82544596641104410931110439544807341718861383747637169079459650724829233712960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/76.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4188835648 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/76.uart_fifo_reset.4188835648 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 76.uart_fifo_reset.4188835648 -covoverwrite' seed=82544596641104410931110439544807341718861383747637169079459650724829233712960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82544596641104410931110439544807341718861383747637169079459650724829233712960 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/76.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 56554090851560381838867765396561316095458665028350373430234672441226158083101 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/77.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=950209565 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/77.uart_fifo_reset.950209565 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 77.uart_fifo_reset.950209565 -covoverwrite' seed=56554090851560381838867765396561316095458665028350373430234672441226158083101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56554090851560381838867765396561316095458665028350373430234672441226158083101 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/77.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 21991786562637960915842394219663376974122357121843430267634290226273164024699 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/78.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1626692475 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/78.uart_fifo_reset.1626692475 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 78.uart_fifo_reset.1626692475 -covoverwrite' seed=21991786562637960915842394219663376974122357121843430267634290226273164024699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21991786562637960915842394219663376974122357121843430267634290226273164024699 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/78.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 32657286714738674968789457294675152447232292799457611986872075413759779740372 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/79.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=112794324 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/79.uart_fifo_reset.112794324 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 79.uart_fifo_reset.112794324 -covoverwrite' seed=32657286714738674968789457294675152447232292799457611986872075413759779740372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32657286714738674968789457294675152447232292799457611986872075413759779740372 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/79.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 109691408740415568500510411256048751755219264687998461988272749490630961996261 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/80.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=767107557 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/80.uart_fifo_reset.767107557 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 80.uart_fifo_reset.767107557 -covoverwrite' seed=109691408740415568500510411256048751755219264687998461988272749490630961996261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109691408740415568500510411256048751755219264687998461988272749490630961996261 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/80.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 46588763517140410019170921019079607014896704602747658210704395860159183682053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/81.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3844045317 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/81.uart_fifo_reset.3844045317 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 81.uart_fifo_reset.3844045317 -covoverwrite' seed=46588763517140410019170921019079607014896704602747658210704395860159183682053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46588763517140410019170921019079607014896704602747658210704395860159183682053 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/81.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 102437369854054117416937719562660491839549524519454779238299337179055960432344 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/82.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=902110936 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/82.uart_fifo_reset.902110936 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 82.uart_fifo_reset.902110936 -covoverwrite' seed=102437369854054117416937719562660491839549524519454779238299337179055960432344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102437369854054117416937719562660491839549524519454779238299337179055960432344 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/82.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 4330214985275604368710811248409711442682130719331983779985503668510169060444 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/83.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3637597276 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/83.uart_fifo_reset.3637597276 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 83.uart_fifo_reset.3637597276 -covoverwrite' seed=4330214985275604368710811248409711442682130719331983779985503668510169060444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4330214985275604368710811248409711442682130719331983779985503668510169060444 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/83.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 56344609717021847088189150189382662180852007111296388852078445882606626384139 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/84.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1014343947 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/84.uart_fifo_reset.1014343947 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 84.uart_fifo_reset.1014343947 -covoverwrite' seed=56344609717021847088189150189382662180852007111296388852078445882606626384139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56344609717021847088189150189382662180852007111296388852078445882606626384139 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/84.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 52106227379768960022172370488285204472387939827657410564744983349173388264158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/85.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4011541214 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/85.uart_fifo_reset.4011541214 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 85.uart_fifo_reset.4011541214 -covoverwrite' seed=52106227379768960022172370488285204472387939827657410564744983349173388264158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52106227379768960022172370488285204472387939827657410564744983349173388264158 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/85.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 16385523962182221851139236506812754454231010206703675603575320016603366749212 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/86.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=895677468 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/86.uart_fifo_reset.895677468 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 86.uart_fifo_reset.895677468 -covoverwrite' seed=16385523962182221851139236506812754454231010206703675603575320016603366749212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16385523962182221851139236506812754454231010206703675603575320016603366749212 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/86.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 106176098330847741508934021452502907459493652762666765059972982016071287170159 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/87.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=6022255 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/87.uart_fifo_reset.6022255 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 87.uart_fifo_reset.6022255 -covoverwrite' seed=106176098330847741508934021452502907459493652762666765059972982016071287170159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106176098330847741508934021452502907459493652762666765059972982016071287170159 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/87.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 39012940429960389256137862352472252345475187909663084463291494739559850928940 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/88.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4283132716 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/88.uart_fifo_reset.4283132716 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 88.uart_fifo_reset.4283132716 -covoverwrite' seed=39012940429960389256137862352472252345475187909663084463291494739559850928940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39012940429960389256137862352472252345475187909663084463291494739559850928940 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/88.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 57177750478739111150787720027043224572040168470805480226560117194137490689259 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/89.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=316935403 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/89.uart_fifo_reset.316935403 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 89.uart_fifo_reset.316935403 -covoverwrite' seed=57177750478739111150787720027043224572040168470805480226560117194137490689259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57177750478739111150787720027043224572040168470805480226560117194137490689259 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/89.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 16980984193601600571679895940455189719921928930556328760830517957883844339178 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/90.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3294602730 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/90.uart_fifo_reset.3294602730 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 90.uart_fifo_reset.3294602730 -covoverwrite' seed=16980984193601600571679895940455189719921928930556328760830517957883844339178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16980984193601600571679895940455189719921928930556328760830517957883844339178 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/90.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 51561132123422097858879422984057298667662424538475286894392282009485359808060 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/91.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2550758972 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/91.uart_fifo_reset.2550758972 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 91.uart_fifo_reset.2550758972 -covoverwrite' seed=51561132123422097858879422984057298667662424538475286894392282009485359808060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51561132123422097858879422984057298667662424538475286894392282009485359808060 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/91.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 51433792560220571114320188398702429924638892569628572121528623970720670777481 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/92.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=397639817 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/92.uart_fifo_reset.397639817 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 92.uart_fifo_reset.397639817 -covoverwrite' seed=51433792560220571114320188398702429924638892569628572121528623970720670777481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51433792560220571114320188398702429924638892569628572121528623970720670777481 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/92.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 21939266921917226637107897169055824807116274463731622002958524997499859242076 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/93.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1519127644 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/93.uart_fifo_reset.1519127644 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 93.uart_fifo_reset.1519127644 -covoverwrite' seed=21939266921917226637107897169055824807116274463731622002958524997499859242076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21939266921917226637107897169055824807116274463731622002958524997499859242076 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/93.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 89933861756567205303312340201641726089433860727094678788113593762960026070126 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/94.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2798087278 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/94.uart_fifo_reset.2798087278 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 94.uart_fifo_reset.2798087278 -covoverwrite' seed=89933861756567205303312340201641726089433860727094678788113593762960026070126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89933861756567205303312340201641726089433860727094678788113593762960026070126 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/94.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 93770448084564891098959193103513963831441790487582412510039496311779732252386 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/95.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1875142370 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/95.uart_fifo_reset.1875142370 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 95.uart_fifo_reset.1875142370 -covoverwrite' seed=93770448084564891098959193103513963831441790487582412510039496311779732252386 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93770448084564891098959193103513963831441790487582412510039496311779732252386 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/95.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 74445913201695594555385251233499288373438436966285061300096007796786597083623 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/96.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2776775143 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/96.uart_fifo_reset.2776775143 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 96.uart_fifo_reset.2776775143 -covoverwrite' seed=74445913201695594555385251233499288373438436966285061300096007796786597083623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74445913201695594555385251233499288373438436966285061300096007796786597083623 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/96.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 107003053314092995347692370671525281942637029767259105460208508441020032861729 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/97.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2114700833 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/97.uart_fifo_reset.2114700833 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 97.uart_fifo_reset.2114700833 -covoverwrite' seed=107003053314092995347692370671525281942637029767259105460208508441020032861729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107003053314092995347692370671525281942637029767259105460208508441020032861729 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/97.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 30628904085472516296447064986417507605011527853539048170876261093237472362634 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/98.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=289144970 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/98.uart_fifo_reset.289144970 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 98.uart_fifo_reset.289144970 -covoverwrite' seed=30628904085472516296447064986417507605011527853539048170876261093237472362634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30628904085472516296447064986417507605011527853539048170876261093237472362634 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/98.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 565355132174922408318820190286341789930689541342441251120615147424424502018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/99.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=202482434 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/99.uart_fifo_reset.202482434 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 99.uart_fifo_reset.202482434 -covoverwrite' seed=565355132174922408318820190286341789930689541342441251120615147424424502018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=565355132174922408318820190286341789930689541342441251120615147424424502018 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/99.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 39673909486061923587498404345838615933825346528724890783145685292938387322176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/100.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2225927488 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/100.uart_fifo_reset.2225927488 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 100.uart_fifo_reset.2225927488 -covoverwrite' seed=39673909486061923587498404345838615933825346528724890783145685292938387322176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39673909486061923587498404345838615933825346528724890783145685292938387322176 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/100.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 19964254054387418539180999154623191187830343282447411111297928800656730874759 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/101.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2298209159 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/101.uart_fifo_reset.2298209159 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 101.uart_fifo_reset.2298209159 -covoverwrite' seed=19964254054387418539180999154623191187830343282447411111297928800656730874759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19964254054387418539180999154623191187830343282447411111297928800656730874759 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/101.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 107638107941435492087492932048754210942317854055477290100244382208267597764841 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/102.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3761363177 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/102.uart_fifo_reset.3761363177 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 102.uart_fifo_reset.3761363177 -covoverwrite' seed=107638107941435492087492932048754210942317854055477290100244382208267597764841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107638107941435492087492932048754210942317854055477290100244382208267597764841 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/102.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 95090733106896723171759089404641426938454170989339954073090064432604017379746 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/103.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1899022754 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/103.uart_fifo_reset.1899022754 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 103.uart_fifo_reset.1899022754 -covoverwrite' seed=95090733106896723171759089404641426938454170989339954073090064432604017379746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95090733106896723171759089404641426938454170989339954073090064432604017379746 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/103.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 74603312053460604652277345154109958059618970872838635939885007958277123030184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/104.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3582278824 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/104.uart_fifo_reset.3582278824 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 104.uart_fifo_reset.3582278824 -covoverwrite' seed=74603312053460604652277345154109958059618970872838635939885007958277123030184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74603312053460604652277345154109958059618970872838635939885007958277123030184 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/104.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 30950817097432950758467419426602000347928231470006709138536137228359569214007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/105.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2581301815 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/105.uart_fifo_reset.2581301815 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 105.uart_fifo_reset.2581301815 -covoverwrite' seed=30950817097432950758467419426602000347928231470006709138536137228359569214007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30950817097432950758467419426602000347928231470006709138536137228359569214007 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/105.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 20624859165046237986902589630642603358451421823639258757476312279508832656576 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/106.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2980748480 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/106.uart_fifo_reset.2980748480 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 106.uart_fifo_reset.2980748480 -covoverwrite' seed=20624859165046237986902589630642603358451421823639258757476312279508832656576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20624859165046237986902589630642603358451421823639258757476312279508832656576 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/106.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 336285807952353107448915217648415358163130160306369264285122280328750236964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/107.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4135650596 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/107.uart_fifo_reset.4135650596 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 107.uart_fifo_reset.4135650596 -covoverwrite' seed=336285807952353107448915217648415358163130160306369264285122280328750236964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=336285807952353107448915217648415358163130160306369264285122280328750236964 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/107.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 100425430296936222748294266418735660764604088192332556689945443410664384899638 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/108.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=84683318 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/108.uart_fifo_reset.84683318 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 108.uart_fifo_reset.84683318 -covoverwrite' seed=100425430296936222748294266418735660764604088192332556689945443410664384899638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100425430296936222748294266418735660764604088192332556689945443410664384899638 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/108.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 67140815768404929593780210519103085142434032568915090778224201431479816088082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/109.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4106545682 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/109.uart_fifo_reset.4106545682 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 109.uart_fifo_reset.4106545682 -covoverwrite' seed=67140815768404929593780210519103085142434032568915090778224201431479816088082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67140815768404929593780210519103085142434032568915090778224201431479816088082 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/109.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 26307173974625614066804332311088081121358828190997592984697633340678945757927 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/110.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3164723943 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/110.uart_fifo_reset.3164723943 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 110.uart_fifo_reset.3164723943 -covoverwrite' seed=26307173974625614066804332311088081121358828190997592984697633340678945757927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26307173974625614066804332311088081121358828190997592984697633340678945757927 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/110.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 20878197726123349976071272206052399042993540093184981547719536788576625729948 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/111.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2483003804 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/111.uart_fifo_reset.2483003804 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 111.uart_fifo_reset.2483003804 -covoverwrite' seed=20878197726123349976071272206052399042993540093184981547719536788576625729948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20878197726123349976071272206052399042993540093184981547719536788576625729948 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/111.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 33074988621430510121301905216688513320649401853948221205100492945735412505378 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/112.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3808320290 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/112.uart_fifo_reset.3808320290 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 112.uart_fifo_reset.3808320290 -covoverwrite' seed=33074988621430510121301905216688513320649401853948221205100492945735412505378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33074988621430510121301905216688513320649401853948221205100492945735412505378 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/112.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 63179837240604450105707298551158192638864821248112304327527019173805724229686 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/113.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=745234486 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/113.uart_fifo_reset.745234486 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 113.uart_fifo_reset.745234486 -covoverwrite' seed=63179837240604450105707298551158192638864821248112304327527019173805724229686 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63179837240604450105707298551158192638864821248112304327527019173805724229686 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/113.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 38174828323033306238480244435002414471311674416855824849809373696336633298364 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/114.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4069031356 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/114.uart_fifo_reset.4069031356 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 114.uart_fifo_reset.4069031356 -covoverwrite' seed=38174828323033306238480244435002414471311674416855824849809373696336633298364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38174828323033306238480244435002414471311674416855824849809373696336633298364 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/114.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 7125505359684382431106487268523447102203440901896858557024907205560968900406 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/115.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2639228726 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/115.uart_fifo_reset.2639228726 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 115.uart_fifo_reset.2639228726 -covoverwrite' seed=7125505359684382431106487268523447102203440901896858557024907205560968900406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7125505359684382431106487268523447102203440901896858557024907205560968900406 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/115.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 96100458788316545077664718293440158211762284724294121963902053724917549251040 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/116.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3914611168 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/116.uart_fifo_reset.3914611168 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 116.uart_fifo_reset.3914611168 -covoverwrite' seed=96100458788316545077664718293440158211762284724294121963902053724917549251040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96100458788316545077664718293440158211762284724294121963902053724917549251040 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/116.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 14382001875993902150501139570159078830289884901039026197886683261834130408338 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/117.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=925156242 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/117.uart_fifo_reset.925156242 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 117.uart_fifo_reset.925156242 -covoverwrite' seed=14382001875993902150501139570159078830289884901039026197886683261834130408338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14382001875993902150501139570159078830289884901039026197886683261834130408338 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/117.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 49942192956584333605872484899317051191380196104993220879190501215493086051617 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/118.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3303603489 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/118.uart_fifo_reset.3303603489 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 118.uart_fifo_reset.3303603489 -covoverwrite' seed=49942192956584333605872484899317051191380196104993220879190501215493086051617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49942192956584333605872484899317051191380196104993220879190501215493086051617 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/118.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 25206972438645577680504280127372319423681217159720747489018771970276853854412 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/119.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2159063244 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/119.uart_fifo_reset.2159063244 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 119.uart_fifo_reset.2159063244 -covoverwrite' seed=25206972438645577680504280127372319423681217159720747489018771970276853854412 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25206972438645577680504280127372319423681217159720747489018771970276853854412 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/119.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 28497850502904453781228336126845297506188830287917340409340128584491369868428 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/120.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2116660364 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/120.uart_fifo_reset.2116660364 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 120.uart_fifo_reset.2116660364 -covoverwrite' seed=28497850502904453781228336126845297506188830287917340409340128584491369868428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28497850502904453781228336126845297506188830287917340409340128584491369868428 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/120.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 43860240176616046211036144906329734411213953201195670911897505683960613714576 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/121.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=532822672 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/121.uart_fifo_reset.532822672 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 121.uart_fifo_reset.532822672 -covoverwrite' seed=43860240176616046211036144906329734411213953201195670911897505683960613714576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43860240176616046211036144906329734411213953201195670911897505683960613714576 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/121.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 76170199648488682066858833318718654534280241308856695248969999184672031908429 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/122.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1828594253 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/122.uart_fifo_reset.1828594253 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 122.uart_fifo_reset.1828594253 -covoverwrite' seed=76170199648488682066858833318718654534280241308856695248969999184672031908429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76170199648488682066858833318718654534280241308856695248969999184672031908429 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/122.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 50118676839846213384302725243077643548100640618367970279683293336728870266920 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/123.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3188664360 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/123.uart_fifo_reset.3188664360 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 123.uart_fifo_reset.3188664360 -covoverwrite' seed=50118676839846213384302725243077643548100640618367970279683293336728870266920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50118676839846213384302725243077643548100640618367970279683293336728870266920 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/123.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 58416603754694220719232452055283719373434977907951831504226253482586068253239 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/124.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4087380535 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/124.uart_fifo_reset.4087380535 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 124.uart_fifo_reset.4087380535 -covoverwrite' seed=58416603754694220719232452055283719373434977907951831504226253482586068253239 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58416603754694220719232452055283719373434977907951831504226253482586068253239 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/124.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 61373440598789050794110668071239523042494679557991531039415061097519483334369 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/125.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1509043937 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/125.uart_fifo_reset.1509043937 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 125.uart_fifo_reset.1509043937 -covoverwrite' seed=61373440598789050794110668071239523042494679557991531039415061097519483334369 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61373440598789050794110668071239523042494679557991531039415061097519483334369 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/125.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 22094924020804247806017204946984894425651987775411569969900528050535391654683 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/126.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1101624091 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/126.uart_fifo_reset.1101624091 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 126.uart_fifo_reset.1101624091 -covoverwrite' seed=22094924020804247806017204946984894425651987775411569969900528050535391654683 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22094924020804247806017204946984894425651987775411569969900528050535391654683 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/126.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 13406403438443572325357269651739633412891014433420976422763413274226998697946 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/127.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3655393242 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/127.uart_fifo_reset.3655393242 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 127.uart_fifo_reset.3655393242 -covoverwrite' seed=13406403438443572325357269651739633412891014433420976422763413274226998697946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13406403438443572325357269651739633412891014433420976422763413274226998697946 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/127.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 31113884452457248114269418071027343489083222375074975005692716770715594518787 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/128.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3805933827 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/128.uart_fifo_reset.3805933827 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 128.uart_fifo_reset.3805933827 -covoverwrite' seed=31113884452457248114269418071027343489083222375074975005692716770715594518787 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31113884452457248114269418071027343489083222375074975005692716770715594518787 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/128.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 84148880358983291731042193052884142576582986122338919853307848150250316631059 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/129.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=22285331 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/129.uart_fifo_reset.22285331 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 129.uart_fifo_reset.22285331 -covoverwrite' seed=84148880358983291731042193052884142576582986122338919853307848150250316631059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84148880358983291731042193052884142576582986122338919853307848150250316631059 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/129.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 73876697015360088876146016952329735710397327652370172344441150549715194820379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/130.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=360527643 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/130.uart_fifo_reset.360527643 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 130.uart_fifo_reset.360527643 -covoverwrite' seed=73876697015360088876146016952329735710397327652370172344441150549715194820379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73876697015360088876146016952329735710397327652370172344441150549715194820379 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/130.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 92615108664504302646929680670485604249669434447141213788716990878796799909742 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/131.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4159283054 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/131.uart_fifo_reset.4159283054 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 131.uart_fifo_reset.4159283054 -covoverwrite' seed=92615108664504302646929680670485604249669434447141213788716990878796799909742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92615108664504302646929680670485604249669434447141213788716990878796799909742 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/131.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 69330764388737210103361873221986358532738813214683643143866877443442491901088 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/132.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4074882208 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/132.uart_fifo_reset.4074882208 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 132.uart_fifo_reset.4074882208 -covoverwrite' seed=69330764388737210103361873221986358532738813214683643143866877443442491901088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69330764388737210103361873221986358532738813214683643143866877443442491901088 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/132.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 40359875049288447123777058519598372722287996061994017692597814486424813106414 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/133.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1863382254 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/133.uart_fifo_reset.1863382254 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 133.uart_fifo_reset.1863382254 -covoverwrite' seed=40359875049288447123777058519598372722287996061994017692597814486424813106414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40359875049288447123777058519598372722287996061994017692597814486424813106414 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/133.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 33814742632786076716015460994360694254338328405536026375718748226310307154018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/134.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1582139490 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/134.uart_fifo_reset.1582139490 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 134.uart_fifo_reset.1582139490 -covoverwrite' seed=33814742632786076716015460994360694254338328405536026375718748226310307154018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33814742632786076716015460994360694254338328405536026375718748226310307154018 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/134.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 34447541516101787530637884289543755203156520120069584498945798464263298412756 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/135.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=656601300 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/135.uart_fifo_reset.656601300 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 135.uart_fifo_reset.656601300 -covoverwrite' seed=34447541516101787530637884289543755203156520120069584498945798464263298412756 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34447541516101787530637884289543755203156520120069584498945798464263298412756 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/135.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 16397392336353309862094123117244208081181761056792318097163592170345822297216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/136.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1921916032 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/136.uart_fifo_reset.1921916032 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 136.uart_fifo_reset.1921916032 -covoverwrite' seed=16397392336353309862094123117244208081181761056792318097163592170345822297216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16397392336353309862094123117244208081181761056792318097163592170345822297216 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/136.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 41955391914752561229038660324720984202928399553675006938790246451466552050328 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/137.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2567799448 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/137.uart_fifo_reset.2567799448 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 137.uart_fifo_reset.2567799448 -covoverwrite' seed=41955391914752561229038660324720984202928399553675006938790246451466552050328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41955391914752561229038660324720984202928399553675006938790246451466552050328 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/137.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 4332106818200812237806564279159029398057381226006562733949839978717725381424 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/138.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3636253488 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/138.uart_fifo_reset.3636253488 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 138.uart_fifo_reset.3636253488 -covoverwrite' seed=4332106818200812237806564279159029398057381226006562733949839978717725381424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4332106818200812237806564279159029398057381226006562733949839978717725381424 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/138.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 22979715074179015111634419311963913195423430574618443996825758993931865837018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/139.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1917734362 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/139.uart_fifo_reset.1917734362 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 139.uart_fifo_reset.1917734362 -covoverwrite' seed=22979715074179015111634419311963913195423430574618443996825758993931865837018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22979715074179015111634419311963913195423430574618443996825758993931865837018 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/139.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 103370268275788011801566682905325457144866668632090732652737053400044478873867 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/140.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2357936395 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/140.uart_fifo_reset.2357936395 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 140.uart_fifo_reset.2357936395 -covoverwrite' seed=103370268275788011801566682905325457144866668632090732652737053400044478873867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103370268275788011801566682905325457144866668632090732652737053400044478873867 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/140.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 82301501149035237526828537233028205269467811835887444488615332646708345647086 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/141.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2363568110 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/141.uart_fifo_reset.2363568110 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 141.uart_fifo_reset.2363568110 -covoverwrite' seed=82301501149035237526828537233028205269467811835887444488615332646708345647086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82301501149035237526828537233028205269467811835887444488615332646708345647086 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/141.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 68691960551180143534598514653718795408685225717251970015318688622201070193574 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/142.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=181701542 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/142.uart_fifo_reset.181701542 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 142.uart_fifo_reset.181701542 -covoverwrite' seed=68691960551180143534598514653718795408685225717251970015318688622201070193574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68691960551180143534598514653718795408685225717251970015318688622201070193574 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/142.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 1110546633172265663748836056750861449095215914774297509710833295403129271513 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/143.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2901701849 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/143.uart_fifo_reset.2901701849 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 143.uart_fifo_reset.2901701849 -covoverwrite' seed=1110546633172265663748836056750861449095215914774297509710833295403129271513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1110546633172265663748836056750861449095215914774297509710833295403129271513 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/143.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 85617071823140601952983944624685404006391328709889381668507280248267745856498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/144.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2171931634 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/144.uart_fifo_reset.2171931634 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 144.uart_fifo_reset.2171931634 -covoverwrite' seed=85617071823140601952983944624685404006391328709889381668507280248267745856498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85617071823140601952983944624685404006391328709889381668507280248267745856498 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/144.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 25655722733545795218299656558161460714712575821227141001838361082903549372387 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/145.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1300162531 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/145.uart_fifo_reset.1300162531 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 145.uart_fifo_reset.1300162531 -covoverwrite' seed=25655722733545795218299656558161460714712575821227141001838361082903549372387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25655722733545795218299656558161460714712575821227141001838361082903549372387 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/145.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 5372155515152273244689241372355264358270421576444280779426784989606517403412 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/146.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3458199316 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/146.uart_fifo_reset.3458199316 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 146.uart_fifo_reset.3458199316 -covoverwrite' seed=5372155515152273244689241372355264358270421576444280779426784989606517403412 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5372155515152273244689241372355264358270421576444280779426784989606517403412 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/146.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 87991795490536431829662486180347039401017660439591932335591964566172406071849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/147.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=64700969 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/147.uart_fifo_reset.64700969 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 147.uart_fifo_reset.64700969 -covoverwrite' seed=87991795490536431829662486180347039401017660439591932335591964566172406071849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87991795490536431829662486180347039401017660439591932335591964566172406071849 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/147.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 115505850955111915299023267436078566705692207006669483955701499148487669284342 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/148.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=275217910 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/148.uart_fifo_reset.275217910 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 148.uart_fifo_reset.275217910 -covoverwrite' seed=115505850955111915299023267436078566705692207006669483955701499148487669284342 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115505850955111915299023267436078566705692207006669483955701499148487669284342 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/148.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 49055562145721416057338101894045003292952439083905065849837811069364971577606 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/149.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2934513926 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/149.uart_fifo_reset.2934513926 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 149.uart_fifo_reset.2934513926 -covoverwrite' seed=49055562145721416057338101894045003292952439083905065849837811069364971577606 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49055562145721416057338101894045003292952439083905065849837811069364971577606 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/149.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 67003646774031620270801885957594944887995921297378247158696076181082017369856 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/150.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=31461120 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/150.uart_fifo_reset.31461120 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 150.uart_fifo_reset.31461120 -covoverwrite' seed=67003646774031620270801885957594944887995921297378247158696076181082017369856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67003646774031620270801885957594944887995921297378247158696076181082017369856 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/150.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 109646656319450466499664382050211101441809451246493761244378915321087883696222 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/151.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1172527198 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/151.uart_fifo_reset.1172527198 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 151.uart_fifo_reset.1172527198 -covoverwrite' seed=109646656319450466499664382050211101441809451246493761244378915321087883696222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109646656319450466499664382050211101441809451246493761244378915321087883696222 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/151.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 61311639713624439867583519256225948501078687328036991214202704724773631970187 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/152.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2993179531 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/152.uart_fifo_reset.2993179531 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 152.uart_fifo_reset.2993179531 -covoverwrite' seed=61311639713624439867583519256225948501078687328036991214202704724773631970187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61311639713624439867583519256225948501078687328036991214202704724773631970187 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/152.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 63104664938478735492548289318265086776861396243011049850399048972328096861888 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/153.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1227198144 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/153.uart_fifo_reset.1227198144 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 153.uart_fifo_reset.1227198144 -covoverwrite' seed=63104664938478735492548289318265086776861396243011049850399048972328096861888 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63104664938478735492548289318265086776861396243011049850399048972328096861888 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/153.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 99831681520299595433783421657766812180044183856534778660184193180075375258472 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/154.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3368872808 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/154.uart_fifo_reset.3368872808 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 154.uart_fifo_reset.3368872808 -covoverwrite' seed=99831681520299595433783421657766812180044183856534778660184193180075375258472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99831681520299595433783421657766812180044183856534778660184193180075375258472 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/154.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 99497450000709110854369655290046175885698621897904861996468092127590339585012 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/155.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1317282804 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/155.uart_fifo_reset.1317282804 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 155.uart_fifo_reset.1317282804 -covoverwrite' seed=99497450000709110854369655290046175885698621897904861996468092127590339585012 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99497450000709110854369655290046175885698621897904861996468092127590339585012 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/155.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 110760378835381329506989750865306499807273018382106957949027240255369979776301 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/156.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3400682797 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/156.uart_fifo_reset.3400682797 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 156.uart_fifo_reset.3400682797 -covoverwrite' seed=110760378835381329506989750865306499807273018382106957949027240255369979776301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110760378835381329506989750865306499807273018382106957949027240255369979776301 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/156.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 76571410707363073335784984567496895924082270397662254140537266880959686697272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/157.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1840570680 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/157.uart_fifo_reset.1840570680 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 157.uart_fifo_reset.1840570680 -covoverwrite' seed=76571410707363073335784984567496895924082270397662254140537266880959686697272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76571410707363073335784984567496895924082270397662254140537266880959686697272 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/157.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 28839340291647559619029263227134496793973043769521426836759692258741599497269 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/158.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4289621045 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/158.uart_fifo_reset.4289621045 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 158.uart_fifo_reset.4289621045 -covoverwrite' seed=28839340291647559619029263227134496793973043769521426836759692258741599497269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28839340291647559619029263227134496793973043769521426836759692258741599497269 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/158.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 54570126695055472362897115774164246570730933620957439715993448852353873754895 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/159.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3892460303 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/159.uart_fifo_reset.3892460303 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 159.uart_fifo_reset.3892460303 -covoverwrite' seed=54570126695055472362897115774164246570730933620957439715993448852353873754895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54570126695055472362897115774164246570730933620957439715993448852353873754895 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/159.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 60329081786488984182623141848908284946602117911966871713207275285747051744754 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/160.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=154881522 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/160.uart_fifo_reset.154881522 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 160.uart_fifo_reset.154881522 -covoverwrite' seed=60329081786488984182623141848908284946602117911966871713207275285747051744754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60329081786488984182623141848908284946602117911966871713207275285747051744754 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/160.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 107003651590159567461111174725678698316367116546521686420443621245806176112377 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/161.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3923775225 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/161.uart_fifo_reset.3923775225 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 161.uart_fifo_reset.3923775225 -covoverwrite' seed=107003651590159567461111174725678698316367116546521686420443621245806176112377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107003651590159567461111174725678698316367116546521686420443621245806176112377 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/161.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 57445803015497281310702956140863672091869194265689713758466558417703292361608 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/162.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1003477896 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/162.uart_fifo_reset.1003477896 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 162.uart_fifo_reset.1003477896 -covoverwrite' seed=57445803015497281310702956140863672091869194265689713758466558417703292361608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57445803015497281310702956140863672091869194265689713758466558417703292361608 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/162.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 6040236385498536843744331513209364845804184879107618010848805281764231107742 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/163.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=211309726 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/163.uart_fifo_reset.211309726 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 163.uart_fifo_reset.211309726 -covoverwrite' seed=6040236385498536843744331513209364845804184879107618010848805281764231107742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6040236385498536843744331513209364845804184879107618010848805281764231107742 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/163.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 11643182466280978063077196784240024691774580990665549980729997120509260642879 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/164.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1308670527 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/164.uart_fifo_reset.1308670527 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 164.uart_fifo_reset.1308670527 -covoverwrite' seed=11643182466280978063077196784240024691774580990665549980729997120509260642879 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11643182466280978063077196784240024691774580990665549980729997120509260642879 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/164.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 36790532155376017530075895897024624828532008822933661214807636053331580432027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/165.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=436874907 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/165.uart_fifo_reset.436874907 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 165.uart_fifo_reset.436874907 -covoverwrite' seed=36790532155376017530075895897024624828532008822933661214807636053331580432027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36790532155376017530075895897024624828532008822933661214807636053331580432027 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/165.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 10781937800806502611189241488605418477722549645722309501403066660578813376963 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/166.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2403170755 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/166.uart_fifo_reset.2403170755 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 166.uart_fifo_reset.2403170755 -covoverwrite' seed=10781937800806502611189241488605418477722549645722309501403066660578813376963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10781937800806502611189241488605418477722549645722309501403066660578813376963 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/166.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 94279833921937186702411604501544960721626288592596151225987827608020727577268 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/167.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1223113396 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/167.uart_fifo_reset.1223113396 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 167.uart_fifo_reset.1223113396 -covoverwrite' seed=94279833921937186702411604501544960721626288592596151225987827608020727577268 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94279833921937186702411604501544960721626288592596151225987827608020727577268 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/167.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 47962512821106444441412089478888012229399429073920930482197058282471094351721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/168.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=493483881 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/168.uart_fifo_reset.493483881 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 168.uart_fifo_reset.493483881 -covoverwrite' seed=47962512821106444441412089478888012229399429073920930482197058282471094351721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47962512821106444441412089478888012229399429073920930482197058282471094351721 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/168.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 80024752330979142924515447423274424516618990133088637918246638643431857194227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/169.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=382993651 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/169.uart_fifo_reset.382993651 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 169.uart_fifo_reset.382993651 -covoverwrite' seed=80024752330979142924515447423274424516618990133088637918246638643431857194227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80024752330979142924515447423274424516618990133088637918246638643431857194227 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/169.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 5635002685388421109855471192136879581256082379670019615533250372629982403860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/170.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3492338964 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/170.uart_fifo_reset.3492338964 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 170.uart_fifo_reset.3492338964 -covoverwrite' seed=5635002685388421109855471192136879581256082379670019615533250372629982403860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5635002685388421109855471192136879581256082379670019615533250372629982403860 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/170.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 47365884980782169859458259516734883397524758324510934685286798928831458009285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/171.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1505190085 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/171.uart_fifo_reset.1505190085 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 171.uart_fifo_reset.1505190085 -covoverwrite' seed=47365884980782169859458259516734883397524758324510934685286798928831458009285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47365884980782169859458259516734883397524758324510934685286798928831458009285 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/171.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 12234627186124187819762778504389562147227391752943679929340285962699438419597 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/172.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=830074509 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/172.uart_fifo_reset.830074509 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 172.uart_fifo_reset.830074509 -covoverwrite' seed=12234627186124187819762778504389562147227391752943679929340285962699438419597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12234627186124187819762778504389562147227391752943679929340285962699438419597 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/172.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 60506497946443271215545895366676602975944380340375337677577484601189208802932 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/173.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2601109108 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/173.uart_fifo_reset.2601109108 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 173.uart_fifo_reset.2601109108 -covoverwrite' seed=60506497946443271215545895366676602975944380340375337677577484601189208802932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60506497946443271215545895366676602975944380340375337677577484601189208802932 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/173.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 106987783650265511931699074163835620756093384713455675736709145496419123446967 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/174.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2833630391 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/174.uart_fifo_reset.2833630391 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 174.uart_fifo_reset.2833630391 -covoverwrite' seed=106987783650265511931699074163835620756093384713455675736709145496419123446967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106987783650265511931699074163835620756093384713455675736709145496419123446967 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/174.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 78364016458971874312753419042278726855961644081688689321023736214221933679668 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/175.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1787728948 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/175.uart_fifo_reset.1787728948 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 175.uart_fifo_reset.1787728948 -covoverwrite' seed=78364016458971874312753419042278726855961644081688689321023736214221933679668 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78364016458971874312753419042278726855961644081688689321023736214221933679668 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/175.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 100001854741079644600787864186532544160591211091540384819159772042302450175803 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/176.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=102371131 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/176.uart_fifo_reset.102371131 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 176.uart_fifo_reset.102371131 -covoverwrite' seed=100001854741079644600787864186532544160591211091540384819159772042302450175803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100001854741079644600787864186532544160591211091540384819159772042302450175803 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/176.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 66098851964664701674166936906305279390360813820807231955182299498761270697643 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/177.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2066587307 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/177.uart_fifo_reset.2066587307 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 177.uart_fifo_reset.2066587307 -covoverwrite' seed=66098851964664701674166936906305279390360813820807231955182299498761270697643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66098851964664701674166936906305279390360813820807231955182299498761270697643 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/177.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 63314269072509055861648179381738175212068214592567220522990610343347258425771 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/178.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3746857387 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/178.uart_fifo_reset.3746857387 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 178.uart_fifo_reset.3746857387 -covoverwrite' seed=63314269072509055861648179381738175212068214592567220522990610343347258425771 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63314269072509055861648179381738175212068214592567220522990610343347258425771 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/178.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 47637516375647423035076194687847545521829986625616338759157849003875826550521 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/179.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2789623545 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/179.uart_fifo_reset.2789623545 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 179.uart_fifo_reset.2789623545 -covoverwrite' seed=47637516375647423035076194687847545521829986625616338759157849003875826550521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47637516375647423035076194687847545521829986625616338759157849003875826550521 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/179.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 32636857274174584802535586078487335724997961025731831394823286594238429344010 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/180.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=469577994 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/180.uart_fifo_reset.469577994 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 180.uart_fifo_reset.469577994 -covoverwrite' seed=32636857274174584802535586078487335724997961025731831394823286594238429344010 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32636857274174584802535586078487335724997961025731831394823286594238429344010 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/180.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 35420847265458849975833680299524788874312288526581225594138214716660779513371 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/181.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2840000027 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/181.uart_fifo_reset.2840000027 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 181.uart_fifo_reset.2840000027 -covoverwrite' seed=35420847265458849975833680299524788874312288526581225594138214716660779513371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35420847265458849975833680299524788874312288526581225594138214716660779513371 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/181.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 21009652757463261789891927553052959903104668136003537778735861117854619115407 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/182.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4121796495 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/182.uart_fifo_reset.4121796495 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 182.uart_fifo_reset.4121796495 -covoverwrite' seed=21009652757463261789891927553052959903104668136003537778735861117854619115407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21009652757463261789891927553052959903104668136003537778735861117854619115407 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/182.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 26548783371609219856072521333494316183384822594331094440943808354477057797641 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/183.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=66874889 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/183.uart_fifo_reset.66874889 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 183.uart_fifo_reset.66874889 -covoverwrite' seed=26548783371609219856072521333494316183384822594331094440943808354477057797641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26548783371609219856072521333494316183384822594331094440943808354477057797641 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/183.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 85838657068165463138132266463315152979621910021576053946945873087391531345991 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/184.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2122131527 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/184.uart_fifo_reset.2122131527 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 184.uart_fifo_reset.2122131527 -covoverwrite' seed=85838657068165463138132266463315152979621910021576053946945873087391531345991 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85838657068165463138132266463315152979621910021576053946945873087391531345991 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/184.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 16489748126585103854982256376989404339376885316934559134861744512527110256517 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/185.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1733310341 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/185.uart_fifo_reset.1733310341 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 185.uart_fifo_reset.1733310341 -covoverwrite' seed=16489748126585103854982256376989404339376885316934559134861744512527110256517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16489748126585103854982256376989404339376885316934559134861744512527110256517 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/185.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 53035084846920372488771257907708661548211006459000350255845442213295687098471 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/186.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1758879847 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/186.uart_fifo_reset.1758879847 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 186.uart_fifo_reset.1758879847 -covoverwrite' seed=53035084846920372488771257907708661548211006459000350255845442213295687098471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53035084846920372488771257907708661548211006459000350255845442213295687098471 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/186.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 55763854544945454639173750243062049148423214455261883838806072526163689464063 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/187.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3208241407 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/187.uart_fifo_reset.3208241407 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 187.uart_fifo_reset.3208241407 -covoverwrite' seed=55763854544945454639173750243062049148423214455261883838806072526163689464063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55763854544945454639173750243062049148423214455261883838806072526163689464063 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/187.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 38359142056317754288434682604937131341767307279846900590116140169621846971124 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/188.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2827834100 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/188.uart_fifo_reset.2827834100 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 188.uart_fifo_reset.2827834100 -covoverwrite' seed=38359142056317754288434682604937131341767307279846900590116140169621846971124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38359142056317754288434682604937131341767307279846900590116140169621846971124 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/188.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 96509516401607452453426234194966855283650260268152246944996808717071660420206 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/189.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4180479086 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/189.uart_fifo_reset.4180479086 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 189.uart_fifo_reset.4180479086 -covoverwrite' seed=96509516401607452453426234194966855283650260268152246944996808717071660420206 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96509516401607452453426234194966855283650260268152246944996808717071660420206 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/189.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 26608946434628466362966041749902546508596538419481531202101305083558751659327 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/190.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2850579775 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/190.uart_fifo_reset.2850579775 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 190.uart_fifo_reset.2850579775 -covoverwrite' seed=26608946434628466362966041749902546508596538419481531202101305083558751659327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26608946434628466362966041749902546508596538419481531202101305083558751659327 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/190.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 36459581697010040843640298087707527317793218848559645295132585167754266981237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/191.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4127765365 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/191.uart_fifo_reset.4127765365 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 191.uart_fifo_reset.4127765365 -covoverwrite' seed=36459581697010040843640298087707527317793218848559645295132585167754266981237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36459581697010040843640298087707527317793218848559645295132585167754266981237 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/191.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 93833791671638958107653933345545596627381533311017217716257830519855806283983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/192.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3961651407 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/192.uart_fifo_reset.3961651407 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 192.uart_fifo_reset.3961651407 -covoverwrite' seed=93833791671638958107653933345545596627381533311017217716257830519855806283983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93833791671638958107653933345545596627381533311017217716257830519855806283983 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/192.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 62695144927427690252521074987735922037146505839859527594666112003496918484641 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/193.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=4157965985 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/193.uart_fifo_reset.4157965985 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 193.uart_fifo_reset.4157965985 -covoverwrite' seed=62695144927427690252521074987735922037146505839859527594666112003496918484641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62695144927427690252521074987735922037146505839859527594666112003496918484641 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/193.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 18875875083329418112608290050550129901535158678300973536218002726077551409861 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/194.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1530723013 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/194.uart_fifo_reset.1530723013 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 194.uart_fifo_reset.1530723013 -covoverwrite' seed=18875875083329418112608290050550129901535158678300973536218002726077551409861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18875875083329418112608290050550129901535158678300973536218002726077551409861 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/194.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 9734088440629721103075502240020778858498607399497569571699823697880822819576 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/195.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1654369016 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/195.uart_fifo_reset.1654369016 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 195.uart_fifo_reset.1654369016 -covoverwrite' seed=9734088440629721103075502240020778858498607399497569571699823697880822819576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9734088440629721103075502240020778858498607399497569571699823697880822819576 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/195.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 54800245811691303808155566014761057207439414867542258377288053926988552145899 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/196.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=3499428843 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/196.uart_fifo_reset.3499428843 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 196.uart_fifo_reset.3499428843 -covoverwrite' seed=54800245811691303808155566014761057207439414867542258377288053926988552145899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54800245811691303808155566014761057207439414867542258377288053926988552145899 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/196.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 44668441419482912519681031398598486541706387877191287603045576739611179743468 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/197.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=2327312620 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/197.uart_fifo_reset.2327312620 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 197.uart_fifo_reset.2327312620 -covoverwrite' seed=44668441419482912519681031398598486541706387877191287603045576739611179743468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44668441419482912519681031398598486541706387877191287603045576739611179743468 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/197.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 31290165302823591477248872753623857491910176756167769250709275460893107227081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/198.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=73337289 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/198.uart_fifo_reset.73337289 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 198.uart_fifo_reset.73337289 -covoverwrite' seed=31290165302823591477248872753623857491910176756167769250709275460893107227081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31290165302823591477248872753623857491910176756167769250709275460893107227081 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/198.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
uart_fifo_reset 44117375765074730983156011340464297742997870233383089352630522612075318182225 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/uart-sim-xcelium/199.uart_fifo_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/uart-sim-xcelium/default/xcelium.d -r tb +SVSEED=1036222801 +UVM_TESTNAME=uart_base_test +UVM_TEST_SEQ=uart_fifo_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage/default/199.uart_fifo_reset.1036222801 -covworkdir /nightly/current_run/scratch/master/uart-sim-xcelium/coverage -covscope default -covtest 199.uart_fifo_reset.1036222801 -covoverwrite' seed=44117375765074730983156011340464297742997870233383089352630522612075318182225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44117375765074730983156011340464297742997870233383089352630522612075318182225 --run-dir=/nightly/current_run/scratch/master/uart-sim-xcelium/199.uart_fifo_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=uart_base_test uvm_test_seq=uart_fifo_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
uart None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
uart None None