| V1 |
|
98.11% |
| V2 |
|
97.73% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| ac_range_check_smoke | 19 | 20 | 95.00 | |||
| ac_range_check_smoke | 43.000s | 6965.819us | 19 | 20 | 95.00 | |
| ac_range_check_smoke_racl | 20 | 20 | 100.00 | |||
| ac_range_check_smoke_racl | 65.000s | 17008.842us | 20 | 20 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| ac_range_check_csr_hw_reset | 3.000s | 137.466us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| ac_range_check_csr_rw | 3.000s | 176.252us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| ac_range_check_csr_bit_bash | 32.000s | 725.186us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| ac_range_check_csr_aliasing | 7.000s | 258.305us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| ac_range_check_csr_mem_rw_with_rand_reset | 3.000s | 101.239us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| ac_range_check_csr_rw | 3.000s | 176.252us | 5 | 5 | 100.00 | |
| ac_range_check_csr_aliasing | 7.000s | 258.305us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| ac_range_check_lock_range | 20 | 20 | 100.00 | |||
| ac_range_check_lock_range | 4.000s | 264.671us | 20 | 20 | 100.00 | |
| ac_range_bypass_enable | 1 | 1 | 100.00 | |||
| ac_range_check_bypass | 34.000s | 2864.377us | 1 | 1 | 100.00 | |
| stress_all | 8 | 10 | 80.00 | |||
| ac_range_check_stress_all | 286.000s | 15585.447us | 8 | 10 | 80.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| ac_range_check_alert_test | 34.000s | 68.603us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| ac_range_check_intr_test | 2.000s | 26.691us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| ac_range_check_tl_errors | 9.000s | 99.025us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| ac_range_check_tl_errors | 9.000s | 99.025us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| ac_range_check_csr_hw_reset | 3.000s | 137.466us | 1 | 1 | 100.00 | |
| ac_range_check_csr_rw | 3.000s | 176.252us | 5 | 5 | 100.00 | |
| ac_range_check_csr_aliasing | 7.000s | 258.305us | 1 | 1 | 100.00 | |
| ac_range_check_same_csr_outstanding | 6.000s | 286.179us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| ac_range_check_csr_hw_reset | 3.000s | 137.466us | 1 | 1 | 100.00 | |
| ac_range_check_csr_rw | 3.000s | 176.252us | 5 | 5 | 100.00 | |
| ac_range_check_csr_aliasing | 7.000s | 258.305us | 1 | 1 | 100.00 | |
| ac_range_check_same_csr_outstanding | 6.000s | 286.179us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors | 22.000s | 15451.477us | 20 | 20 | 100.00 | |
| shadow_reg_read_clear_staged_value | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors | 22.000s | 15451.477us | 20 | 20 | 100.00 | |
| shadow_reg_storage_error | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors | 22.000s | 15451.477us | 20 | 20 | 100.00 | |
| shadowed_reset_glitch | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors | 22.000s | 15451.477us | 20 | 20 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 20 | 20 | 100.00 | |||
| ac_range_check_shadow_reg_errors_with_csr_rw | 120.000s | 9052.446us | 20 | 20 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| ac_range_check_sec_cm | 2.000s | 38.486us | 5 | 5 | 100.00 | |
| ac_range_check_tl_intg_err | 12.000s | 5394.144us | 25 | 25 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 10 | 10 | 100.00 | |||
| ac_range_check_stress_all_with_rand_reset | 364.000s | 4305.847us | 10 | 10 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 20 | 20 | 100.00 | |||
| ac_range_check_smoke_high_threshold | 42.000s | 4240.165us | 20 | 20 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state | 3 test runs | |||
| ac_range_check_stress_all | 72138376218195969025354420122644575422286727824111654706701737915678062763179 | 13863 |
UVM_INFO @ 4464422193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ac_range_check_stress_all | 62709013169262280627792741897133775795103427299984691549777257112948451501430 | 21705 |
UVM_INFO @ 5111110117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| ac_range_check_smoke | 57523064777118703390021543175253105399898758851901064945745578494186856123478 | 4208 |
UVM_INFO @ 866913667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|