Simulation Results

Simulation Results: clkmgr

04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.38 %

code
70.05 %

assert
90.29 %

func
74.80 %

line
82.42 %

branch
87.53 %

cond
80.31 %

toggle
100.00 %

FSM
0.00 %

Validation stages

V1		65.22%
V2		68.38%
V2S		35.24%
V3		0.00%

15/23 passed

65.22 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	5.390s	319.725us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.300s	25.413us	1	1	100.00
csr_rw				2	5	40.00
	clkmgr_csr_rw	1.850s	63.370us	2	5	40.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	1.600s	17.546us	0	1	0.00
csr_aliasing				0	1	0.00
	clkmgr_csr_aliasing	1.080s	8.538us	0	1	0.00
csr_mem_rw_with_rand_reset				2	5	40.00
	clkmgr_csr_mem_rw_with_rand_reset	3.170s	125.761us	2	5	40.00
regwen_csr_and_corresponding_lockable_csr				2	6	33.33
	clkmgr_csr_rw	1.850s	63.370us	2	5	40.00
	clkmgr_csr_aliasing	1.080s	8.538us	0	1	0.00

80/117 passed

68.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.970s	75.992us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	3.260s	153.540us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.680s	58.085us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	5.390s	319.725us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.110s	11.278us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.180s	16.933us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.110s	11.278us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	4.100s	297.280us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	2.040s	69.233us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	9.920s	490.829us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	9.920s	490.829us	25	25	100.00
tl_d_outstanding_access				4	12	33.33
	clkmgr_csr_hw_reset	1.300s	25.413us	1	1	100.00
	clkmgr_csr_rw	1.850s	63.370us	2	5	40.00
	clkmgr_csr_aliasing	1.080s	8.538us	0	1	0.00
	clkmgr_same_csr_outstanding	1.430s	33.120us	1	5	20.00
tl_d_partial_access				4	12	33.33
	clkmgr_csr_hw_reset	1.300s	25.413us	1	1	100.00
	clkmgr_csr_rw	1.850s	63.370us	2	5	40.00
	clkmgr_csr_aliasing	1.080s	8.538us	0	1	0.00
	clkmgr_same_csr_outstanding	1.430s	33.120us	1	5	20.00

V2S

37/105 passed

35.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				5	30	16.67
	clkmgr_sec_cm	10.390s	777.330us	5	5	100.00
	clkmgr_tl_intg_err	3.590s	178.873us	0	25	0.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	5.510s	306.525us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	5.510s	306.525us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	5.510s	306.525us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	5.510s	306.525us	20	20	100.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	2.910s	145.469us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	3.590s	178.873us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.110s	11.278us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.180s	16.933us	0	10	0.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	5.510s	306.525us	20	20	100.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	2.610s	111.358us	10	10	100.00
sec_cm_jitter_config_mubi				2	5	40.00
	clkmgr_csr_rw	1.850s	63.370us	2	5	40.00
sec_cm_idle_ctr_redun				5	5	100.00
	clkmgr_sec_cm	10.390s	777.330us	5	5	100.00
sec_cm_meas_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.850s	63.370us	2	5	40.00
sec_cm_clk_ctrl_config_regwen				2	5	40.00
	clkmgr_csr_rw	1.850s	63.370us	2	5	40.00
prim_count_check				5	5	100.00
	clkmgr_sec_cm	10.390s	777.330us	5	5	100.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.410s	32.382us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	56.700s	4365.723us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				31 test runs
	clkmgr_tl_intg_err	58552498287723028316815247171503405955106654618447502530913123215506768056747	102	UVM_INFO @ 47653423 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	62092152769655049659298334462709865031873439744610666685494809936990398804121	81	UVM_INFO @ 3015219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_aliasing	70026607670541166204013041121107604130416537526815488362971377443751238835818	83	UVM_INFO @ 8537698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	7757952731844295550174073416594325051877611745522431873678686091452655110430	82	UVM_INFO @ 17889226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	84779789158035328165331460947278004802625463345387333326867870432888653631824	81	UVM_INFO @ 14407686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	18405360333731915866835156462638717172384687039325436357620021444897372950734	81	UVM_INFO @ 10328226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	84660852123874241790987735702608605466377638978509568113117339380234155502363	81	UVM_INFO @ 20674992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	90071842567751142681981149641125720191144640113170309342218426455839784465257	88	UVM_INFO @ 63802786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	15967804420339801272969287963426111977540184743779670312254628148340442613273	81	UVM_INFO @ 12859852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	70528833063351099249076619275543865940727428283226464244203149455598964168694	81	UVM_INFO @ 2597695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	88660936708940521933761673412382931869845528142515480756435628219168361559813	100	UVM_INFO @ 16857295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	85177781024958072139219851492829533585387591760421370037306943448777306732182	81	UVM_INFO @ 3751660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	31717732601099677472172741285927565418245297094998365413020793708902549058610	84	UVM_INFO @ 6892636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	113232380012345624248407671325374500579941986181892495238634119322387439141397	81	UVM_INFO @ 4922787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	33572837897477109710351764390555523445137455067958105579196157955544172618623	91	UVM_INFO @ 12828527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	111240773819059543793058645181593893386663833372416660314525039815352196332535	81	UVM_INFO @ 21151133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	72865769599958631568302863103616153261424533651992079873280814727851602196627	81	UVM_INFO @ 9616772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	99958811893579575341835875369546446452002487360644972703262625982022817486813	81	UVM_INFO @ 12001386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	1742181741343560872718699568204501565496293448436085558976489277758669239555	89	UVM_INFO @ 22307470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	76024184592599241625984360328404640894300849042149306654181310274020736566847	81	UVM_INFO @ 7215976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	73792151945758112435044537658482977113530725878654492320272854440425987134706	103	UVM_INFO @ 31470643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	50517375327879481124224076498376236630194404699252869468570663850046872310960	81	UVM_INFO @ 12430568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	102651522592618368073111991684235216992398193064051627096773934013250501360218	81	UVM_INFO @ 2697769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	49209817720357888996726728067202583609719100328894716068642224972560257081192	92	UVM_INFO @ 13132419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	65170566708107835546802130159048727313923080979163555336855961008541677660507	99	UVM_INFO @ 19174693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	38421534314213845129064320088084204950509883708553438843598237262282400367042	100	UVM_INFO @ 178872903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	40689852756106961548780554919688709708772460192644804482394637304010816493868	81	UVM_INFO @ 12680197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	62540414491534684503623680292319463819596589715520360389712546762493758227860	88	UVM_INFO @ 8235014 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	86393828781421213598243816722767864648938695995129543054635817694225111564160	91	UVM_INFO @ 11373110 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	46049392825092818599159353200342255321585050453264819472766143404041636423793	88	UVM_INFO @ 3606483 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	113997807518652866742500022217276741504157757275578497800080798987135178836639	88	UVM_INFO @ 11407332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				22 test runs
	clkmgr_frequency_timeout	20573119458981196199622305540956457361016646649353385603485944102502350035020	84	UVM_INFO @ 4524298 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	21194945197135375407051294496275024087240046343117014365932901237751753074689	104	UVM_INFO @ 186159391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	106854258212906732443282658127990396457879850834388316306166463098175171474479	84	UVM_INFO @ 6856279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	56185411042685625926454219383403522084049505947353202578812288395720163486482	84	UVM_INFO @ 2653007 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	2826834028232285696735690571651822625048835730756556491572919071867009030493	183	UVM_INFO @ 720339620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	62597045172415205268653362992860670771994558624291457681785973731813233666164	84	UVM_INFO @ 16933364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	12963330541652908178817958059296840797940185018805084522511336088742979929571	84	UVM_INFO @ 2858199 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	13199145269991877066208932413788705150857837782414518607745103148957099359770	83	UVM_INFO @ 2340084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	6700027886860524293342758147937893770001230503943518621411625685301432338349	84	UVM_INFO @ 4094432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	9270035375583170981943993430866408505435330992726708657788397993653219843375	477	UVM_INFO @ 228203422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	27622655179442369005235000649547735777931788783541811246391130268029072527765	83	UVM_INFO @ 17351302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	3826398246463659493410422116815242718534561071714154613451471237839257513317	84	UVM_INFO @ 3050400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	29892865791045951862532859937505090104725280854911448725257909880202051671685	85	UVM_INFO @ 18699248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	107944257184327760176125406711201615867108473109877157760716662797780921834182	83	UVM_INFO @ 7817118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	15608886795658966245664240645086676509011579722850520135048723862611819901628	83	UVM_INFO @ 3399386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	55835107991158719382992021821492981161195314161047117938850598095778946865762	84	UVM_INFO @ 6452145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	22530470488592891592163157576758115525601807284196577441123902034909238915032	133	UVM_INFO @ 4365722998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	45740001419458468793174188785457917368976714030213268447600239912829738294514	83	UVM_INFO @ 81145864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	93311787794803487124056327893764358793395204347664596231988327552026358269629	84	UVM_INFO @ 6690393 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	107771700653404134491252788305097063101082647609895260571890430906863380351576	85	UVM_INFO @ 6517488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	41258319539589058122134761912337660270375835688245425523948702352687579778507	84	UVM_INFO @ 1757505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	44152618609544410085928217979728468580706034026987479585240158481925158674768	121	UVM_INFO @ 286860926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				21 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	64728744004399933343450646371518461533747107524103598098063116255711643316919	81	UVM_INFO @ 10357286 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	22871107464066642825334071665480291097091730016909997812976258194796793945112	118	UVM_INFO @ 28625855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	99787292913560807350793491453662124983126105036912915319272640861519348863380	82	UVM_INFO @ 25494413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	64399731241925412019409984238557866688380019956758803071887376970366821460197	81	UVM_INFO @ 35313216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	29275014213236820076082396861469346250328940870663245412652141980608742122004	88	UVM_INFO @ 2612220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	44558291065379085561224089645782200683835222069940365063766278775486359278976	84	UVM_INFO @ 3608318 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	31683994858016419977399359224099516714237612664178265820671874304840195999719	81	UVM_INFO @ 5545214 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	38280898068031966162824268369694366740669938812771122397468555634327348473614	91	UVM_INFO @ 8302500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	37192609657456667515314627211297145280530780978585846470649880774331751746106	81	UVM_INFO @ 1907643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	114238187810045193750076999139578036044559355939568157014100073873653527234620	92	UVM_INFO @ 32063167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	24196004337592301605281260158005799756683313841791988264373348358413914501382	95	UVM_INFO @ 20032620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	85872801094807694735067113610726430106234083874606075696427395099254306698288	81	UVM_INFO @ 2813747 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	12572184956911314934326865904836052967783225839000308023553306289598922087212	81	UVM_INFO @ 145468717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	47466083316779602682686006152839847049566934878837350717879469464638927878351	92	UVM_INFO @ 10292991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	59129589293096479548668364768499826635422061875408480303261961977217675491238	81	UVM_INFO @ 15132733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	4372731255082447017204013541009086383758195474207903316793785629445741017582	85	UVM_INFO @ 7973183 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	89684320454619186714900598717056281029436817852159444862120130319841406333804	104	UVM_INFO @ 21531257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	110241629118750433907295635595313435515661871901562190766846736391078506942675	81	UVM_INFO @ 27053231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	54228437350398961750184679556091902177795359509670471361518298686842295071393	81	UVM_INFO @ 6905663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	49730025700204306794925505949289658867020101832552415354844663044484854658358	88	UVM_INFO @ 12386177 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	98563294643072430428349766232205867178288909821933889566611773316787843087232	89	UVM_INFO @ 7114358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				17 test runs
	clkmgr_frequency	68163849873314563588272818097693427355311179659638591287872072933547729731231	82	UVM_INFO @ 6958547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	65017064221139391312000911948551052404481961289071190854362713642420497858046	82	UVM_INFO @ 8509575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	91874926121686839743153090262123323234295407470425471184601045283790958568063	82	UVM_INFO @ 25241620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	68768886610246522271385018542177107697995063176551858925608337032344638670050	82	UVM_INFO @ 5275998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	83177232751262068014566687674587493064028816488279954901386793584401468970902	132	UVM_INFO @ 65275858 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	4178714673966502108074196456926358476735439534940286197485703275010249323411	117	UVM_INFO @ 95225468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	61182624566532349358014887525227936671836051938401151508649172768051390175020	82	UVM_INFO @ 8777076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	45449211701404698432255140972280579470377585991958530196455020391385157159226	84	UVM_INFO @ 39883160 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	50537860524167934932827907232286435955643325335490667841135513035498722229853	82	UVM_INFO @ 7996670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	30135479379098548127948204971825508813629726914120318726899102866184014532286	82	UVM_INFO @ 6587899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	24973340211403105602039525575684730639083427604692942018555647440013079485178	82	UVM_INFO @ 8426710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	57905333012432473264391686225202729559800590333035835541119234002443419369977	88	UVM_INFO @ 12509509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	88444326236714585177818885995260903440555865105812985333945231801555968340821	81	UVM_INFO @ 17676344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	84074424998602192581134671505464572320294625690730124832064929495633144103868	84	UVM_INFO @ 11277745 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	103699770506758942664474692915337711550208325793595739388819466917025483925866	83	UVM_INFO @ 7187738 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	15990962597489997085561315162621559138590253425455217299488144054628783630358	82	UVM_INFO @ 6865386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	9579891787132468809682468098522650427731274709633699907857051663075052773869	81	UVM_INFO @ 15680075 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				5 test runs
	clkmgr_regwen	22700896806714802499128419624727685107619618494035713638551388432352894385505	80	UVM_INFO @ 4074172 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	48447522671171841582573693130074062500877240039711989683194767999906026928878	80	UVM_INFO @ 5959780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	26868049282650496126820170473336513369207256391741244554322649324770272776203	80	UVM_INFO @ 3416783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	65607223483341830114972399840401625691819110914309636889516594702585301495787	80	UVM_INFO @ 2584015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	25897914974687623009788843819568319227043169102197806418623673968520905365411	80	UVM_INFO @ 3242639 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				4 test runs
	clkmgr_same_csr_outstanding	63323117170545554541714129370696263343554098626593394968199410121782245002035	81	UVM_INFO @ 3078608 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	69013784693680842555278020600402542313052116608594282750442863508032454999945	81	UVM_INFO @ 4965089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	5924535692695794245498738467818739480632862627491292135195597918039246940530	81	UVM_INFO @ 2718395 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	66218239215247494587483980294849145719297307349364052731384422860336821737261	81	UVM_INFO @ 11086974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en				3 test runs
	clkmgr_regwen	65085430324152782605622776139929130189613773500988139043278353335270227729267	80	UVM_INFO @ 32381546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	4451201265091867219826761558159909256493645952474484798600631895135774075119	80	UVM_INFO @ 5982757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	112836227932350799555925274661844544054972108888446955357123366281645624597513	80	UVM_INFO @ 7861032 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				2 test runs
	clkmgr_regwen	14337545564164981003540604241158941801517060165668682698252211006631053948631	80	UVM_INFO @ 21279500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	19949941217778901927568035353258722477298812279496266917411751707494259215332	80	UVM_INFO @ 8759675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	79987419836751777090119417988839199092015588326252554782006912393430768742942	81	UVM_INFO @ 17546317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---