Simulation Results: csrng

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.96 %
  • code
  • 96.27 %
  • assert
  • 97.16 %
  • func
  • 91.44 %
  • block
  • 98.63 %
  • line
  • 99.57 %
  • branch
  • 96.64 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.92%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 5.000s 189.965us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 4.000s 114.925us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 3.000s 44.964us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 8.000s 160.196us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 83.464us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 21.283us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 3.000s 44.964us 5 5 100.00
csrng_csr_aliasing 3.000s 83.464us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
alerts 500 500 100.00
csrng_alert 59.000s 3495.787us 500 500 100.00
err 500 500 100.00
csrng_err 9.000s 88.348us 500 500 100.00
cmds 25 25 100.00
csrng_cmds 285.000s 10553.771us 25 25 100.00
life cycle 25 25 100.00
csrng_cmds 285.000s 10553.771us 25 25 100.00
stress_all 25 25 100.00
csrng_stress_all 1553.000s 68567.058us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 3.000s 41.188us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 5.000s 70.427us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 17.000s 670.465us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 17.000s 670.465us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 4.000s 114.925us 1 1 100.00
csrng_csr_rw 3.000s 44.964us 5 5 100.00
csrng_csr_aliasing 3.000s 83.464us 1 1 100.00
csrng_same_csr_outstanding 5.000s 110.781us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 4.000s 114.925us 1 1 100.00
csrng_csr_rw 3.000s 44.964us 5 5 100.00
csrng_csr_aliasing 3.000s 83.464us 1 1 100.00
csrng_same_csr_outstanding 5.000s 110.781us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
csrng_sec_cm 6.000s 286.213us 5 5 100.00
csrng_tl_intg_err 16.000s 711.853us 24 25 96.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 4.000s 130.758us 25 25 100.00
csrng_csr_rw 3.000s 44.964us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 59.000s 3495.787us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 1553.000s 68567.058us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
csrng_sec_cm 6.000s 286.213us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
csrng_sec_cm 6.000s 286.213us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
csrng_sec_cm 6.000s 286.213us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
csrng_sec_cm 6.000s 286.213us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
csrng_sec_cm 6.000s 286.213us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 59.000s 3495.787us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 1553.000s 68567.058us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 59.000s 3495.787us 500 500 100.00
sec_cm_tile_link_bus_integrity 24 25 96.00
csrng_tl_intg_err 16.000s 711.853us 24 25 96.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
csrng_sec_cm 6.000s 286.213us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
csrng_sec_cm 6.000s 286.213us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 33.000s 1883.912us 200 200 100.00
csrng_err 9.000s 88.348us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 587.000s 31557.215us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 9 test runs
csrng_stress_all_with_rand_reset 57123694121971798742267211319960754397924539694970254610234604162479041061935 190
UVM_INFO @ 1144993986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 103253386772046349615050373764444918461894302257505848937181738373644064274432 176
UVM_INFO @ 1625038081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 84860530215945473951038265206502761364502407644717900924683147544515695273508 172
UVM_INFO @ 4308381229 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 102449021752179256889791929188691377048940892324391802770268248662335769757157 135
UVM_INFO @ 2023464749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 86559938389903012488138380178376826438569609446077340171923766264371171078879 183
UVM_INFO @ 804776729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 42960038802065500662451104308207705232341443727119430377087421062491258267634 253
UVM_INFO @ 31557215102 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 51303855378001215005444166899284221223673249319103793813463997746296847285579 104
UVM_INFO @ 32896544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 101798592992035290383533165308454264883416678796658555079396712772460429673114 246
UVM_INFO @ 15764038773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 32494338552698499448295053130746313563396434044348427001046777792474300069412 117
UVM_INFO @ 22040986 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [csrng_common_vseq] Expected alert (fatal_alert) did not fire in * cycles. 1 test run
csrng_tl_intg_err 97968741587606411492321398018205633248450718935855307750318258468269739960281 204
UVM_INFO @ 945663948 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---