Simulation Results: dma

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.18 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 80.18 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 10.000s 503.990us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 9.000s 6734.340us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 10.000s 607.718us 50 50 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 18.345us 1 1 100.00
csr_rw 5 5 100.00
dma_csr_rw 2.000s 35.459us 5 5 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 13.000s 924.071us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 69.538us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 140.135us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
dma_csr_rw 2.000s 35.459us 5 5 100.00
dma_csr_aliasing 2.000s 69.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 159.000s 20906.218us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 580.000s 33872.574us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 984.000s 511160.527us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 984.000s 511160.527us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 580.000s 33872.574us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1751.000s 470124.714us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 984.000s 511160.527us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 19.000s 4226.586us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 308.000s 37085.677us 3 3 100.00
alert_test 10 10 100.00
dma_alert_test 2.000s 11.220us 10 10 100.00
intr_test 10 10 100.00
dma_intr_test 6.000s 18.695us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
dma_tl_errors 5.000s 109.047us 25 25 100.00
tl_d_illegal_access 25 25 100.00
dma_tl_errors 5.000s 109.047us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
dma_csr_hw_reset 2.000s 18.345us 1 1 100.00
dma_csr_rw 2.000s 35.459us 5 5 100.00
dma_csr_aliasing 2.000s 69.538us 1 1 100.00
dma_same_csr_outstanding 3.000s 112.712us 5 5 100.00
tl_d_partial_access 12 12 100.00
dma_csr_hw_reset 2.000s 18.345us 1 1 100.00
dma_csr_rw 2.000s 35.459us 5 5 100.00
dma_csr_aliasing 2.000s 69.538us 1 1 100.00
dma_same_csr_outstanding 3.000s 112.712us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 39.000s 2222.146us 5 5 100.00
dma_generic_stress 1751.000s 470124.714us 5 5 100.00
dma_handshake_stress 984.000s 511160.527us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 12.000s 1305.709us 15 15 100.00
tl_intg_err 30 30 100.00
dma_tl_intg_err 5.000s 823.602us 25 25 100.00
dma_sec_cm 2.000s 17.761us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 241.000s 53324.078us 25 25 100.00
dma_longer_transfer 21.000s 787.218us 5 5 100.00
dma_stress_all_with_rand_reset 10.000s 940.312us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 108207780647238419354229405504167759856685895622142576471526868708110723692907 96
UVM_INFO @ 940311794ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---