Simulation Results: edn/edn0

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.92 %
  • code
  • 95.31 %
  • assert
  • 97.57 %
  • func
  • 58.88 %
  • block
  • 96.99 %
  • line
  • 98.68 %
  • branch
  • 93.33 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 7.000s 28.662us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 17.089us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 65.215us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.000s 155.794us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 45.989us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 3.000s 38.623us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 65.215us 5 5 100.00
edn_csr_aliasing 2.000s 45.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 10.000s 765.801us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 10.000s 765.801us 100 100 100.00
genbits 100 100 100.00
edn_genbits 10.000s 765.801us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 27.348us 20 20 100.00
alerts 200 200 100.00
edn_alert 3.000s 30.186us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 64.714us 100 100 100.00
disable 100 100 100.00
edn_disable 2.000s 32.649us 50 50 100.00
edn_disable_auto_req_mode 3.000s 44.425us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 9.000s 375.893us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 39.123us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 168.897us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.000s 509.341us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.000s 509.341us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 17.089us 1 1 100.00
edn_csr_rw 2.000s 65.215us 5 5 100.00
edn_csr_aliasing 2.000s 45.989us 1 1 100.00
edn_same_csr_outstanding 3.000s 113.739us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 17.089us 1 1 100.00
edn_csr_rw 2.000s 65.215us 5 5 100.00
edn_csr_aliasing 2.000s 45.989us 1 1 100.00
edn_same_csr_outstanding 3.000s 113.739us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 14.000s 3877.860us 5 5 100.00
edn_tl_intg_err 6.000s 453.915us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 40.312us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 3.000s 30.186us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 14.000s 3877.860us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 14.000s 3877.860us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 14.000s 3877.860us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 14.000s 3877.860us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 3.000s 30.186us 200 200 100.00
edn_sec_cm 14.000s 3877.860us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 3.000s 30.186us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 6.000s 453.915us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 30 100.00
edn_stress_all_with_rand_reset 137.000s 5463.789us 30 30 100.00