Simulation Results: edn/edn1

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.58 %
  • code
  • 95.66 %
  • assert
  • 98.44 %
  • func
  • 92.65 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.77 %
  • toggle
  • 96.15 %
  • FSM
  • 94.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
99.57%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.330s 19.740us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.130s 93.875us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.240s 23.676us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.100s 809.432us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.250s 52.747us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 1.870s 23.976us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.240s 23.676us 5 5 100.00
edn_csr_aliasing 1.250s 52.747us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 3.950s 222.627us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 3.950s 222.627us 100 100 100.00
genbits 100 100 100.00
edn_genbits 3.950s 222.627us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.420s 23.614us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.810s 341.161us 200 200 100.00
errs 100 100 100.00
edn_err 1.750s 36.161us 100 100 100.00
disable 100 100 100.00
edn_disable 1.260s 15.084us 50 50 100.00
edn_disable_auto_req_mode 1.810s 68.642us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 8.240s 497.926us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.260s 66.108us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.960s 142.367us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.430s 140.369us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.430s 140.369us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.130s 93.875us 1 1 100.00
edn_csr_rw 1.240s 23.676us 5 5 100.00
edn_csr_aliasing 1.250s 52.747us 1 1 100.00
edn_same_csr_outstanding 1.690s 94.994us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.130s 93.875us 1 1 100.00
edn_csr_rw 1.240s 23.676us 5 5 100.00
edn_csr_aliasing 1.250s 52.747us 1 1 100.00
edn_same_csr_outstanding 1.690s 94.994us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 29 30 96.67
edn_sec_cm 6.770s 430.936us 4 5 80.00
edn_tl_intg_err 5.230s 281.722us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.320s 18.872us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.810s 341.161us 200 200 100.00
sec_cm_main_sm_fsm_sparse 4 5 80.00
edn_sec_cm 6.770s 430.936us 4 5 80.00
sec_cm_ack_sm_fsm_sparse 4 5 80.00
edn_sec_cm 6.770s 430.936us 4 5 80.00
sec_cm_fifo_ctr_redun 4 5 80.00
edn_sec_cm 6.770s 430.936us 4 5 80.00
sec_cm_ctr_redun 4 5 80.00
edn_sec_cm 6.770s 430.936us 4 5 80.00
sec_cm_main_sm_ctr_local_esc 204 205 99.51
edn_alert 1.810s 341.161us 200 200 100.00
edn_sec_cm 6.770s 430.936us 4 5 80.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.810s 341.161us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 5.230s 281.722us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 30 100.00
edn_stress_all_with_rand_reset 135.270s 19181.562us 30 30 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1057) virtual_sequencer [edn_common_vseq] Expected alert (fatal_alert) did not fire in * cycles. 1 test run
edn_sec_cm 36150721957491141572142283324603498309881358567942975687747550186009724616223 121
UVM_INFO @ 310249307 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---