| V1 |
|
100.00% |
| V2 |
|
93.63% |
| V2S |
|
96.67% |
| V3 |
|
40.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 2.180s | 89.472us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 2.180s | 85.956us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 2.210s | 84.228us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 2.070s | 89.201us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.070s | 32.419us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 1.100s | 79.201us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 4.190s | 754.297us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.190s | 56.230us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.480s | 75.732us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 1.100s | 79.201us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.190s | 56.230us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 2.050s | 133.842us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 2.020s | 76.710us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.480s | 30.656us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 2.060s | 54.648us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 5.200s | 183.848us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 3.670s | 145.031us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 22.780s | 4525.910us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 7.040s | 3636.374us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.580s | 137.017us | 10 | 10 | 100.00 | |
| stress_all | 0 | 10 | 0.00 | |||
| gpio_stress_all | 79.560s | 6084.719us | 0 | 10 | 0.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.910s | 123.313us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 1.010s | 19.559us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.130s | 737.415us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.130s | 737.415us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| gpio_csr_rw | 1.100s | 79.201us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.910s | 35.436us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.190s | 56.230us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.070s | 32.419us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| gpio_csr_rw | 1.100s | 79.201us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.910s | 35.436us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.190s | 56.230us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.070s | 32.419us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 29 | 30 | 96.67 | |||
| gpio_tl_intg_err | 3.600s | 698.076us | 24 | 25 | 96.00 | |
| gpio_sec_cm | 1.340s | 90.933us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 24 | 25 | 96.00 | |||
| gpio_tl_intg_err | 3.600s | 698.076us | 24 | 25 | 96.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 8 | 10 | 80.00 | |||
| gpio_rand_straps | 0.930s | 14.155us | 8 | 10 | 80.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 13.820s | 5215.518us | 0 | 10 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 50 | 50 | 100.00 | |||
| gpio_inp_prd_cnt | 0.950s | 33.582us | 50 | 50 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:243) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 12 test runs | |||
| gpio_stress_all | 42721187213759947328579056099375251955439223255086274872118720625519599429366 | 82 |
UVM_INFO @ 381320566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 64643451087632508293587643885520893604637281903578295241911846719291978814028 | 81 |
UVM_INFO @ 2578419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 99329236015610661273236295043100961704185714207219983537485780795965514251918 | 1338 |
UVM_INFO @ 43363171625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 114704829741831251561836373467573166690703639246551228884667175173848397903505 | 83 |
UVM_INFO @ 2351430931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 16339990451622070895613832201441580849070026654014506383939047063287170875170 | 343 |
UVM_INFO @ 7041277969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_rand_straps | 91043439628326691822664726483224260345933524426430596697915343276559951297875 | 81 |
UVM_INFO @ 2202676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 113638512667473426359447694286322803165559598405023556897795390464465173743358 | 390 |
UVM_INFO @ 941888434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 84148711404120710791150232590535580561692092353205853109296228231303703396265 | 398 |
UVM_INFO @ 12874268617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 41556930937428394098253198012357576596176647672422462786747348700013502347695 | 342 |
UVM_INFO @ 2645806862 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 51546489211441449664289230434330197036909935254371118096769274000008158327371 | 567 |
UVM_INFO @ 24004566203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 8074971823008041357911880025198302982250756498127510282942367229392225294814 | 1891 |
UVM_INFO @ 6084719216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 43319505913322437554228971201573614721464007507912997138103332651885925908770 | 83 |
UVM_INFO @ 338806668 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1230) [gpio_common_vseq] Check failed (vseq_done) | 6 test runs | |||
| gpio_stress_all_with_rand_reset | 6163773523849756303158846631318410455374750785923627231942952748030410125603 | 290 |
UVM_INFO @ 2361961024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 53332963722200063057752589263525559856521350466980467271422949884139990264901 | 143 |
UVM_INFO @ 5215518054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 104399214938847891933570177079703062446186143483636820767677564179097432803204 | 121 |
UVM_INFO @ 836999847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 58519720981423218006312973226372001028641165198359896126080745676438511821999 | 202 |
UVM_INFO @ 546628937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 47425317350828150588571394238998102474296778291827198517229102637336337142348 | 93 |
UVM_INFO @ 47950489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 54322408823547955288930276176045270319400348722515343984782388217396175747129 | 86 |
UVM_INFO @ 8373256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 4 test runs | |||
| gpio_stress_all_with_rand_reset | 13449939297448259510291007704855821238389427934530164427324981066706267584636 | 85 |
UVM_INFO @ 162574817 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 28848424649482854717320868251346034327835791534526260989494225374500239261735 | 84 |
UVM_INFO @ 10403605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 29224376133174755843749276217808910586409982164050264138689416595646145402220 | 86 |
UVM_INFO @ 489913548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 90045990225219734702954745905106852168032337368447101292668320851558149932552 | 86 |
UVM_INFO @ 1056247372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_val_* reset value: * | 1 test run | |||
| gpio_tl_intg_err | 112317952873097097628577587429385703965474751863140569024867616501303255502405 | 91 |
UVM_INFO @ 10990932 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|