Simulation Results: hmac

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.51 %
  • code
  • 83.35 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 23.000s 6332.520us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 31.024us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 406.291us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.000s 2850.343us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 153.852us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 1327.000s 132554.675us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 406.291us 5 5 100.00
hmac_csr_aliasing 2.000s 153.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 125.000s 17352.581us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 123.000s 3292.748us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 383.000s 11001.874us 30 30 100.00
hmac_test_sha384_vectors 707.000s 72049.772us 75 75 100.00
hmac_test_sha512_vectors 747.000s 41422.320us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 3960.507us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 2050.252us 60 60 100.00
hmac_test_hmac512_vectors 27.000s 543.948us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 54.000s 14963.008us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 353.000s 30784.631us 10 10 100.00
error 10 10 100.00
hmac_error 234.000s 317609.967us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 164.000s 50854.661us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 23.000s 6332.520us 10 10 100.00
hmac_long_msg 125.000s 17352.581us 10 10 100.00
hmac_back_pressure 123.000s 3292.748us 25 25 100.00
hmac_datapath_stress 353.000s 30784.631us 10 10 100.00
hmac_burst_wr 54.000s 14963.008us 50 50 100.00
hmac_stress_all 1241.000s 97470.952us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 23.000s 6332.520us 10 10 100.00
hmac_long_msg 125.000s 17352.581us 10 10 100.00
hmac_back_pressure 123.000s 3292.748us 25 25 100.00
hmac_datapath_stress 353.000s 30784.631us 10 10 100.00
hmac_wipe_secret 164.000s 50854.661us 10 10 100.00
hmac_test_sha256_vectors 383.000s 11001.874us 30 30 100.00
hmac_test_sha384_vectors 707.000s 72049.772us 75 75 100.00
hmac_test_sha512_vectors 747.000s 41422.320us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 3960.507us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 2050.252us 60 60 100.00
hmac_test_hmac512_vectors 27.000s 543.948us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 23.000s 6332.520us 10 10 100.00
hmac_long_msg 125.000s 17352.581us 10 10 100.00
hmac_back_pressure 123.000s 3292.748us 25 25 100.00
hmac_datapath_stress 353.000s 30784.631us 10 10 100.00
hmac_burst_wr 54.000s 14963.008us 50 50 100.00
hmac_error 234.000s 317609.967us 10 10 100.00
hmac_wipe_secret 164.000s 50854.661us 10 10 100.00
hmac_test_sha256_vectors 383.000s 11001.874us 30 30 100.00
hmac_test_sha384_vectors 707.000s 72049.772us 75 75 100.00
hmac_test_sha512_vectors 747.000s 41422.320us 75 75 100.00
hmac_test_hmac256_vectors 22.000s 3960.507us 50 50 100.00
hmac_test_hmac384_vectors 24.000s 2050.252us 60 60 100.00
hmac_test_hmac512_vectors 27.000s 543.948us 75 75 100.00
hmac_stress_all 1241.000s 97470.952us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1241.000s 97470.952us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 20.539us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 49.335us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 6.000s 935.829us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 6.000s 935.829us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 31.024us 1 1 100.00
hmac_csr_rw 2.000s 406.291us 5 5 100.00
hmac_csr_aliasing 2.000s 153.852us 1 1 100.00
hmac_same_csr_outstanding 3.000s 596.215us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 31.024us 1 1 100.00
hmac_csr_rw 2.000s 406.291us 5 5 100.00
hmac_csr_aliasing 2.000s 153.852us 1 1 100.00
hmac_same_csr_outstanding 3.000s 596.215us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 126.708us 5 5 100.00
hmac_tl_intg_err 6.000s 279.178us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 6.000s 279.178us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 23.000s 6332.520us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 8.000s 472.815us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 764.000s 70085.445us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.000s 100.186us 1 1 100.00