Simulation Results: keymgr_dpe/darjeeling

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 65.87 %
  • code
  • 82.54 %
  • assert
  • 97.20 %
  • func
  • 17.88 %
  • block
  • 98.02 %
  • line
  • 98.66 %
  • branch
  • 93.56 %
  • toggle
  • 56.39 %
  • FSM
  • 81.54 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
keymgr_dpe_smoke 17.000s 4563.155us 10 10 100.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 2.000s 19.313us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 2.000s 17.039us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 7.000s 1254.797us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 1.000s 74.087us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 181.808us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 2.000s 17.039us 5 5 100.00
keymgr_dpe_csr_aliasing 1.000s 74.087us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 23.653us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 2.000s 13.261us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 141.084us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 141.084us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 19.313us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 17.039us 5 5 100.00
keymgr_dpe_csr_aliasing 1.000s 74.087us 1 1 100.00
keymgr_dpe_same_csr_outstanding 6.000s 46.431us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 19.313us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 17.039us 5 5 100.00
keymgr_dpe_csr_aliasing 1.000s 74.087us 1 1 100.00
keymgr_dpe_same_csr_outstanding 6.000s 46.431us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 10.000s 1866.070us 5 5 100.00
keymgr_dpe_tl_intg_err 5.000s 220.880us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 1795.413us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 1795.413us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 1795.413us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 1795.413us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 10.000s 2069.360us 19 20 95.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 10.000s 1866.070us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 10.000s 1866.070us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1391) [keymgr_dpe_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 12968448003064548072216489920017464110051889199797805981967056380258426185344 85
UVM_INFO @ 189730551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---