Simulation Results: rom_ctrl/32kb

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.02 %
  • code
  • 85.09 %
  • assert
  • 97.67 %
  • func
  • 99.29 %
  • block
  • 79.14 %
  • line
  • 79.28 %
  • branch
  • 81.16 %
  • toggle
  • 84.69 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
80.28%
V2S
64.41%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.000s 430.659us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 2.000s 64.876us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 2.000s 63.266us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 78.137us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 64.849us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 62.440us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 2.000s 63.266us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 64.849us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 54.990us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 1.000s 51.498us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 3.000s 388.780us 0 2 0.00
stress_all 9 20 45.00
rom_ctrl_stress_all 10807.000s 0.000us 9 20 45.00
kmac_err_chk 1 2 50.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 1 2 50.00
alert_test 10 10 100.00
rom_ctrl_alert_test 3.000s 53.507us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 228.173us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 7.000s 228.173us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 2.000s 64.876us 1 1 100.00
rom_ctrl_csr_rw 2.000s 63.266us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 64.849us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 72.536us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 2.000s 64.876us 1 1 100.00
rom_ctrl_csr_rw 2.000s 63.266us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 64.849us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 72.536us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 2100.047us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 138.000s 532.293us 5 5 100.00
rom_ctrl_tl_intg_err 36.000s 217.457us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 138.000s 532.293us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 138.000s 532.293us 5 5 100.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 138.000s 532.293us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 138.000s 532.293us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.000s 430.659us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.000s 430.659us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.000s 430.659us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 36.000s 217.457us 25 25 100.00
sec_cm_bus_local_esc 1 22 4.55
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 1 2 50.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 9.000s 2100.047us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 138.000s 532.293us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 20 35.00
rom_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 7 20 35.00

Error Messages

   Test seed line log context
Job timed out after * minutes 37 test runs
rom_ctrl_stress_all 85065717811677148852780881345637079470919320239859098912507643950893456682509 None
rom_ctrl_corrupt_sig_fatal_chk 112841780996872311056663786200375852348176428685985852619042931098326555875852 None
rom_ctrl_stress_all 15241341918694640121221900695313831319288255843829214797199419950767650085262 None
rom_ctrl_corrupt_sig_fatal_chk 95415301757575217363683637122524332385105321061342020615097508936106442233691 None
rom_ctrl_kmac_err_chk 41654114726309252664857335417135012968990638262540922343552684980996315968315 None
rom_ctrl_stress_all_with_rand_reset 72527468818665611726376159027636593796240421851410786111844951552511139213541 None
rom_ctrl_corrupt_sig_fatal_chk 55124370620988377590613760273716853267193735113476405407690171777049095693546 None
rom_ctrl_stress_all 25570187554206256759105149260407071333742236888465675909192723980389927787004 None
rom_ctrl_corrupt_sig_fatal_chk 9199508852671761579092166431259042193193245144398638510258788602164176379991 None
rom_ctrl_corrupt_sig_fatal_chk 13644895415930088941510700897494257480144019079378413128693841233173822720478 None
rom_ctrl_corrupt_sig_fatal_chk 112561530512357710412567054077268935367971126928065270790710822779610191270757 None
rom_ctrl_stress_all 55723470456962080693889539123945315381153281687257187910958132657062633718044 None
rom_ctrl_corrupt_sig_fatal_chk 112557591403810773221385636083597391094359471906087371352706653199016022279437 None
rom_ctrl_stress_all_with_rand_reset 28288580261288220567642388988603536876200656491162668055501741841960115239240 None
rom_ctrl_corrupt_sig_fatal_chk 8196226746923556848112126215306660001559791729531018945980253863169618139133 None
rom_ctrl_stress_all 19074225363515705813548308033785392450577966450232465884048823521667011680436 None
rom_ctrl_corrupt_sig_fatal_chk 49250574078326944494239011597680173471829400988548598928924479074398626607351 None
rom_ctrl_stress_all_with_rand_reset 48371988854489933898532056107636436236039351638619286454218415897981516456351 None
rom_ctrl_stress_all 3669266787612397232287039834172167101393506907912622509525632962645570483490 None
rom_ctrl_corrupt_sig_fatal_chk 41247719218926252307974417441533552794190524361316143357343927848232913273243 None
rom_ctrl_stress_all 1121759301331197955931424179994422531420935313293068144933781151617176414051 None
rom_ctrl_corrupt_sig_fatal_chk 57889991662169741523025951670882826640425196916725790765839616525899573010883 None
rom_ctrl_stress_all 55265124146755110626445811077817784056524379517489448346871244788057369458452 None
rom_ctrl_corrupt_sig_fatal_chk 64381686457511332694913552445705343193995422364316176984895509402139217472345 None
rom_ctrl_corrupt_sig_fatal_chk 52525955188183959746325786929371235514373388774277919031188776741587378646706 None
rom_ctrl_stress_all_with_rand_reset 42100574694059459463165123661981243447744495534895928029405890087913206292694 None
rom_ctrl_stress_all 79100346617684830639233240203426069703987488016505769922151470412600462580220 None
rom_ctrl_corrupt_sig_fatal_chk 61876842390111718545417005838374647587534931807949773797540287972860242889956 None
rom_ctrl_corrupt_sig_fatal_chk 68278258664094957278354463955259663466666117129461890256168220316734901975281 None
rom_ctrl_stress_all 83297701329364659092933003517893586421458416282833803138887873685174978513132 None
rom_ctrl_corrupt_sig_fatal_chk 398295147938202882897504037409459392769955217073072419581064073951178186383 None
rom_ctrl_corrupt_sig_fatal_chk 78953459702175544335502828623136928768933057845463976756349563710488167281993 None
rom_ctrl_stress_all 63342777268184483166585620093743890837128579712017490185120879190525958221876 None
rom_ctrl_corrupt_sig_fatal_chk 81117790172618503123763563794742446977287596963879297252620316560739384182478 None
rom_ctrl_corrupt_sig_fatal_chk 53347009442753900096891904300943670028362748033741165625895573458594453658949 None
rom_ctrl_corrupt_sig_fatal_chk 57255867073039744638887498713559798812633083934061302334320349687108816136649 None
rom_ctrl_stress_all_with_rand_reset 51246406768385301590497478358570482499027968327576966609351011018225799160960 None
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 8 test runs
rom_ctrl_stress_all_with_rand_reset 76630649357591652099776333962691235859303030800050224761004134113334764221212 143
UVM_INFO @ 3237850015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 77379389031592283699932284792162055523736722309061174633304576173487355144882 101
UVM_INFO @ 864369029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 107800131074050688514011296438668487386002101628436420412520588496833426679594 94
UVM_INFO @ 650872135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 96190740262994585561136257743685623915689513819561886583130179619490923555978 94
UVM_INFO @ 525640761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 52864402046525641585110082592978748371293574289854020394138189098085526203672 115
UVM_INFO @ 1227138292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 85248331596697509472242184814647376878066540443610881072513844390527023070165 90
UVM_INFO @ 187380822 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 56988603915714066798927632252066056481772920536105085006357114183301615346272 108
UVM_INFO @ 630883941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 80452528948083814028604363981334175206154921675883575952673071313266916111535 90
UVM_INFO @ 1237759507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 55318710485708758140152808176939979355372814827507163795452920239458938572970 88
UVM_INFO @ 388779956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 63085224802431839784148386421347583581870130513422581428117346694218759503455 88
UVM_INFO @ 333431536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---