Simulation Results: rom_ctrl/64kb

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.67 %
  • code
  • 81.34 %
  • assert
  • 97.38 %
  • func
  • 99.29 %
  • block
  • 78.90 %
  • line
  • 79.19 %
  • branch
  • 80.47 %
  • toggle
  • 84.74 %
  • FSM
  • 80.95 %
Validation stages
V1
100.00%
V2
81.69%
V2S
64.41%
V3
25.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 5.000s 394.374us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 58.524us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 3.000s 78.854us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 139.553us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 59.555us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 281.242us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 3.000s 78.854us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 59.555us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 75.536us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 99.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.000s 468.844us 0 2 0.00
stress_all 10 20 50.00
rom_ctrl_stress_all 10801.000s 0.000us 10 20 50.00
kmac_err_chk 1 2 50.00
rom_ctrl_kmac_err_chk 3601.000s 0.000us 1 2 50.00
alert_test 10 10 100.00
rom_ctrl_alert_test 4.000s 65.586us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 8.000s 371.637us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 8.000s 371.637us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.000s 58.524us 1 1 100.00
rom_ctrl_csr_rw 3.000s 78.854us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 59.555us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 71.611us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.000s 58.524us 1 1 100.00
rom_ctrl_csr_rw 3.000s 78.854us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 59.555us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 71.611us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 2135.562us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 242.000s 3014.743us 5 5 100.00
rom_ctrl_tl_intg_err 60.000s 367.292us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 242.000s 3014.743us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 242.000s 3014.743us 5 5 100.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 242.000s 3014.743us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 242.000s 3014.743us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 5.000s 394.374us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 5.000s 394.374us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 5.000s 394.374us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 60.000s 367.292us 25 25 100.00
sec_cm_bus_local_esc 1 22 4.55
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
rom_ctrl_kmac_err_chk 3601.000s 0.000us 1 2 50.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 20.000s 2135.562us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 242.000s 3014.743us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 5 20 25.00
rom_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 5 20 25.00

Error Messages

   Test seed line log context
Job timed out after * minutes 34 test runs
rom_ctrl_corrupt_sig_fatal_chk 22078472379541861773942984607251387357483195495559714626533051978996690797579 None
rom_ctrl_kmac_err_chk 19518434532133333662203646416077732886118359506961291354252339263096979257598 None
rom_ctrl_stress_all_with_rand_reset 23313698569180550796585048007963224337182606940403833576763360751834767822164 None
rom_ctrl_stress_all 24159914636954314526699903383442003814088281773407070280271523290839079649466 None
rom_ctrl_corrupt_sig_fatal_chk 51865569856977556500006449667573039888537885559610716956926031136824466046697 None
rom_ctrl_corrupt_sig_fatal_chk 97321150518959375715083635003576959679800084503321092461743647905196347285711 None
rom_ctrl_stress_all 33542070210106784755521608620344677747481909147422832291425536911947094587130 None
rom_ctrl_corrupt_sig_fatal_chk 76639833527307616735446239664197108855121003331864706034318285019134102815801 None
rom_ctrl_corrupt_sig_fatal_chk 6064988576749074039316107462244517621547033543928437184313001613591993450379 None
rom_ctrl_corrupt_sig_fatal_chk 78034907297475641771583770280346627839243589332503689467173502577028315108225 None
rom_ctrl_corrupt_sig_fatal_chk 32916652335435199702174277577000754743963168578828686639090281648952010988831 None
rom_ctrl_stress_all 102453832450326886838374607584842252748655573499777387007526068314742702946609 None
rom_ctrl_corrupt_sig_fatal_chk 44584471682704059627028808825114194237067379292674403878477919947192981225642 None
rom_ctrl_corrupt_sig_fatal_chk 47101101099227549526163734559735572835855698611604131428134038946355192883066 None
rom_ctrl_stress_all 80677670347179870942378750867426207681755772448491485452274771432609614370915 None
rom_ctrl_corrupt_sig_fatal_chk 70305203838498814616843416832532217181518987479620939490729227963891695989665 None
rom_ctrl_corrupt_sig_fatal_chk 26324093966841828637993150420856960635396090162059087677028427137388244374090 None
rom_ctrl_corrupt_sig_fatal_chk 69831071608643064454227770509775202874276775387917926701245140089757210769422 None
rom_ctrl_stress_all 82107810206512311999292154205876360691522314686014158650503104482886774684987 None
rom_ctrl_corrupt_sig_fatal_chk 83273579370008727146446302553055280382306768047385782843273891064808148757679 None
rom_ctrl_stress_all 82877342688943741135901764233026479971661955803514608462816977445453139715678 None
rom_ctrl_corrupt_sig_fatal_chk 27736919579361168846599439931605941916166602156385700080003092012207001321148 None
rom_ctrl_corrupt_sig_fatal_chk 36211167831255346611946423448757112417433428627741900960945202559828532682895 None
rom_ctrl_stress_all 54399607418887968698748202382809467555387958163269759878885647697452873180281 None
rom_ctrl_corrupt_sig_fatal_chk 67983664244435776829424690010312976642470760841051696124393442303521243483927 None
rom_ctrl_stress_all 96969350250600624137482297837835708933373949077189262872172840207717524533606 None
rom_ctrl_corrupt_sig_fatal_chk 21782519833166972685984341692839162424249583759991466257852539198775659534104 None
rom_ctrl_stress_all 81509283058825633764899019114622056553532221139399568869884126118503891899508 None
rom_ctrl_corrupt_sig_fatal_chk 85657337998885842864337913520502119622298341216020853115090195277990929876208 None
rom_ctrl_stress_all 45005051321603920382790924232646465376408057538185954165508147596918776875752 None
rom_ctrl_corrupt_sig_fatal_chk 30595381345068221567271431348151517259445574145792606218771843585982447570907 None
rom_ctrl_stress_all_with_rand_reset 62871606128554612545043515436012853514212019958372047946867238062059775625472 None
rom_ctrl_corrupt_sig_fatal_chk 113545577211236040760530316880808824102492802153342229090788079351482526867103 None
rom_ctrl_stress_all_with_rand_reset 16220013769887827573802778637164653183405844241627103326040931248563323595851 None
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 12 test runs
rom_ctrl_stress_all_with_rand_reset 52786432197013087385905003545953563322391118226656119668235491907279284383189 99
UVM_INFO @ 1578982469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 58724955715021165420148001657842494689993075042065580542342407028052425455688 95
UVM_INFO @ 1067426631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 60818098111193583507054207075132937119686702543709232744199532592700101084382 94
UVM_INFO @ 1567984762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 68490482015529098302136750907461976094675879129084683173697886698645528586983 128
UVM_INFO @ 3597368445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 92227370332305778640233531810252674489095915096335107212369056721099927322670 93
UVM_INFO @ 917868652 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 68192479423651836544524790693866783616775045630484262611893345858458952459457 100
UVM_INFO @ 815309871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 73999720212211577082822854306915040012896694951866675386168517148998749972019 89
UVM_INFO @ 133446658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 27320638700194923243468920289130549399301811215455909718971526401858872643334 156
UVM_INFO @ 4228077279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 5022679581285431049654303345660128380530576490869372188370380919408053966705 186
UVM_INFO @ 9459028586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 61976027108744371465902350516405485236341811503666397071180746224505160442405 89
UVM_INFO @ 360913380 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 44396805981355169716837450654963835592512079277069297804825894654692958917348 141
UVM_INFO @ 2420306533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 5364410618905619186825506078466709395344913056160569821842030795440911843124 94
UVM_INFO @ 404842607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 59558294340012945244195458968001381517528065936997852967351266378413731960270 88
UVM_INFO @ 468844463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 21596036979949915605729067604461702596239308925694929238649570444534347191725 88
UVM_INFO @ 9023268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---