Simulation Results

Simulation Results: rv_dm/use_dmi_interface

04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.02 %

code
83.35 %

assert
97.13 %

func
95.57 %

block
93.85 %

line
94.43 %

branch
83.33 %

toggle
75.28 %

FSM
80.36 %

Validation stages

V1		96.92%
V2		44.44%
V2S		86.00%
V3		10.00%
unmapped		0.00%

126/130 passed

96.92 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	48.000s	1075.218us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	52.000s	217.292us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	52.000s	309.411us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	87.000s	24727.880us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	53.000s	573.658us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	70.000s	8561.380us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	88.000s	16667.386us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	142.000s	63238.974us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	89.000s	22169.363us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	52.000s	384.919us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	51.000s	892.439us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	52.000s	603.884us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	52.000s	158.441us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	49.000s	179.076us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	53.000s	2999.470us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	50.000s	70.560us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	55.000s	1324.258us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	52.000s	384.919us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	48.000s	572.028us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	51.000s	536.255us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	52.000s	603.884us	2	2	100.00
rom_read_access				0	2	0.00
	rv_dm_rom_read_access	44.000s	15.706us	0	2	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	49.000s	682.816us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	51.000s	110.968us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	109.000s	9193.516us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	56.000s	2794.700us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	50.000s	178.763us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	56.000s	2794.700us	1	1	100.00
	rv_dm_csr_rw	51.000s	110.968us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	43.000s	53.384us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	50.000s	168.933us	1	1	100.00

80/180 passed

44.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	48.000s	1075.218us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	50.000s	401.128us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	54.000s	232.498us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	51.000s	600.449us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	47.000s	1073.035us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	63.000s	7922.205us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	53.000s	613.560us	0	20	0.00
bad_sba				1	20	5.00
	rv_dm_bad_sba_tl_access	89.000s	15149.542us	1	20	5.00
sba_autoincrement				4	20	20.00
	rv_dm_autoincr_sba_tl_access	191.000s	63826.282us	4	20	20.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	53.000s	318.528us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	50.000s	4658.263us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	53.000s	707.378us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	52.000s	195.507us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	57.000s	19407.118us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	134.000s	11497.227us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	47.000s	325.667us	1	1	100.00
stress_all				2	20	10.00
	rv_dm_stress_all	10801.000s	0.000us	2	20	10.00
alert_test				10	10	100.00
	rv_dm_alert_test	52.000s	132.243us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	54.000s	111.610us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	54.000s	111.610us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	56.000s	2794.700us	1	1	100.00
	rv_dm_csr_hw_reset	49.000s	682.816us	1	1	100.00
	rv_dm_csr_rw	51.000s	110.968us	5	5	100.00
	rv_dm_same_csr_outstanding	55.000s	6503.505us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	56.000s	2794.700us	1	1	100.00
	rv_dm_csr_hw_reset	49.000s	682.816us	1	1	100.00
	rv_dm_csr_rw	51.000s	110.968us	5	5	100.00
	rv_dm_same_csr_outstanding	55.000s	6503.505us	5	5	100.00

V2S

43/50 passed

86.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				27	30	90.00
	rv_dm_sec_cm	52.000s	574.867us	4	5	80.00
	rv_dm_tl_intg_err	73.000s	5517.119us	23	25	92.00
sec_cm_bus_integrity				23	25	92.00
	rv_dm_tl_intg_err	73.000s	5517.119us	23	25	92.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	50.000s	4658.263us	2	2	100.00
	rv_dm_debug_disabled	49.000s	39.467us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	50.000s	4658.263us	2	2	100.00
	rv_dm_debug_disabled	49.000s	39.467us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	48.000s	1075.218us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				6	10	60.00
	rv_dm_buffered_enable	53.000s	592.058us	6	10	60.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	51.000s	300.433us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	51.000s	300.433us	4	4	100.00
sec_cm_exec_ctrl_mubi				6	10	60.00
	rv_dm_buffered_enable	53.000s	592.058us	6	10	60.00

2/20 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	20	10.00
	rv_dm_stress_all_with_rand_reset	73.000s	1754.915us	2	20	10.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	212.000s	300000.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				42 test runs
	rv_dm_sba_tl_access	94550652424960418490236881607914953021761522892486250888149753606757425168847	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23820
	rv_dm_delayed_resp_sba_tl_access	36711058168012690339145188133034162482922785871213740314538430862327344128930	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23836
	rv_dm_sba_tl_access	44508287684233485187685823286640712295042223983423203994965881003654095066163	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23785
	rv_dm_bad_sba_tl_access	31928687711601695640709255513663119074309244162242710970749797046419319401162	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23934
	rv_dm_sba_tl_access	108142186554211893523405724290995821555368808984168813071344794300808682150667	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23794
	rv_dm_bad_sba_tl_access	91586237093775408493389333847538794255738087119065054937166989762891047256818	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23853
	rv_dm_autoincr_sba_tl_access	66577414194420222431036464241898734570383492726466483070099503076867968505437	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24442
	rv_dm_sba_tl_access	17811795390348463844671082837916545808000006704942510039170745486718073899229	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23842
	rv_dm_autoincr_sba_tl_access	53502448005056050479311295371176082881670420014998934737348043038167453707916	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23911
	rv_dm_sba_tl_access	66078138879008577345678956414000078512597815353024037102233842490824232645257	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23817
	rv_dm_bad_sba_tl_access	93650646629900199300532394351546409754204410798195142394102212760089849690656	132	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @25427
	rv_dm_sba_tl_access	19221358622709575726761488569026542420029324921188391624112988509550149194364	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23819
	rv_dm_sba_tl_access	9676672996186305970773459586892204124721154980085827852162973169099537081692	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23879
	rv_dm_bad_sba_tl_access	96073019420452231026186942747365770695039797035635344079600938211216139373244	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23924
	rv_dm_autoincr_sba_tl_access	4923762799373371719035604462507971472327501300556147109507275770928499506265	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23985
	rv_dm_sba_tl_access	63188589584597722697431735535518258549997879790005154990341661045833458752439	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23882
	rv_dm_autoincr_sba_tl_access	38607506150425382810299372593188487653288518537300905735427595762710377317392	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23925
	rv_dm_sba_tl_access	21464862072366839889507583120093510822066654253901097687870058286534719857446	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23794
	rv_dm_bad_sba_tl_access	71036620599673003396966085671908607489990101934796137171396387434641215864899	117	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @25042
	rv_dm_autoincr_sba_tl_access	30435081897565988288473883197625286781135286144848256391873945755156944786584	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23886
	rv_dm_sba_tl_access	29516857654713806118126773385274200044321629878418307983002780769780073301633	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23879
	rv_dm_bad_sba_tl_access	59682757360624604973342830850585271903631173129116801274469332694176191388414	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23792
	rv_dm_autoincr_sba_tl_access	111082092125526787086825837588981546588578907295090356715262835555644207019458	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23837
	rv_dm_sba_tl_access	81774137410502814877978403013746965077861100411815222228990825925849339208541	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23886
	rv_dm_bad_sba_tl_access	85847470267231214843990722596394693308875618383106558563057092398193055028036	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23965
	rv_dm_sba_tl_access	78020171898986555526881130297703000809524938153789104620442650473522803100315	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23841
	rv_dm_bad_sba_tl_access	100014650980665596287637750216448336551581692218165660824836225158288715344067	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23833
	rv_dm_sba_tl_access	28707610554013247191409960543435481468204467444549359032128874137249695301900	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23815
	rv_dm_bad_sba_tl_access	32222145690516359680988739337064691955960390739286500299249382221611594987366	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23790
	rv_dm_sba_tl_access	112880273464041446081578156767659963878174977689310460251961312581956807336630	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23878
	rv_dm_bad_sba_tl_access	107530413830008065667870155184501470913521813756501902364427206944804390175583	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23746
	rv_dm_sba_tl_access	89794328339437138548280439409738648332498690119625005432004470597178771738959	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23836
	rv_dm_sba_tl_access	73354840929773451640570667188656933870395678583404165097122074201321744641733	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23880
	rv_dm_sba_tl_access	51808946203049059137757585393840716235276792037377804977710271417596289125164	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23816
	rv_dm_bad_sba_tl_access	88853378570198958757657510777957659673468440592978855190370104278437573515827	90	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23820
	rv_dm_sba_tl_access	13159081166947721464113690996471929372312683936658178183740262785588053426970	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23826
	rv_dm_sba_tl_access	39555415745128719947448069413439397505470358968335591395981234543540327413364	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23874
	rv_dm_bad_sba_tl_access	47946741352091999342692784266042228102349483361404507322720067836165669207040	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23790
	rv_dm_autoincr_sba_tl_access	47013903446304196548350397824599054543252581412015696380546718590252438738651	159	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24160
	rv_dm_sba_tl_access	75232544146405585921063223587023435871226175932472278011532713392048989469248	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23796
	rv_dm_bad_sba_tl_access	16161256955325076324745330953128163308265275251149077026806980843523016934458	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23861
	rv_dm_autoincr_sba_tl_access	13028704020897983984473150070047807109417527449982245622434168937774232083188	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23786
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				33 test runs
	rv_dm_bad_sba_tl_access	5425135431989093645921409959582893448469460050347821642809321315269070344360	107	UVM_INFO @ 967066803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	16725496279632071754218576198463251273123882608183905690774245525875970245567	107	UVM_INFO @ 137742186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	36603502799523067323992674122936092182352132525612366335733222263691537171661	107	UVM_INFO @ 587807595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	1144692468610988413714072516320034010399189504670789309972464733271402053384	107	UVM_INFO @ 134354094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	50412754490863420999961991309378414033817085152433306813386636994125554771673	107	UVM_INFO @ 38568465 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	79990069486323965433415040237244655491722579552853337590260991359360472787818	107	UVM_INFO @ 72563351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	114370817585649019694428338706184750335338403051970158809105117442363326248610	107	UVM_INFO @ 93075174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	69406121798590693495752233068313058686634010022752586878017806795098877906465	107	UVM_INFO @ 410353510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	45730324787375463143315203541106876218924968875239509446864345205483829834822	107	UVM_INFO @ 465332525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	33141544528635511618632366388398923770347014872423603729923705441730060460800	122	UVM_INFO @ 74021417863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	80710827892307106004757649556982090896732163255371132310809156918289312159369	107	UVM_INFO @ 285550563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	11249993895649695369648976331319222216883594138871621124222137853871089673998	107	UVM_INFO @ 168985967 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	36938516588862334801404782416469448540909472628536583876993464529808435668983	107	UVM_INFO @ 78059716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	96751119777595635263933201109883837383447321938124214473399738039253273620875	107	UVM_INFO @ 72174945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	59875038994058627291495057108448352560679832443689630735792127217523310128033	107	UVM_INFO @ 203538071 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	105392114065608878483786476228044230945188357045991784553685825307217368996568	107	UVM_INFO @ 613560166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	2997702493423057014105231058349788028449059157845904182678352189727494350955	107	UVM_INFO @ 409743942 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	104934725514081224745369963386678489505124459662803933935470500304909439649054	107	UVM_INFO @ 169444471 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	1442858954873672775342470810719143299650295781039988964788798905482094485611	107	UVM_INFO @ 330123474 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	106086391324436083903649222946954116157693772617708955029586626743062019453581	107	UVM_INFO @ 147190466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	114330582009969587740336897391846603947688376931041549528617052997485269556662	107	UVM_INFO @ 691494436 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	5960774958116070433264728887401941133358170451526722337622072998071882375263	107	UVM_INFO @ 115588415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	55693739666913857573949863271053584452702744184067568924667397188691295599400	107	UVM_INFO @ 42398213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	1021288046947784749627475996083785602833737258681076892081180340640350048543	143	UVM_INFO @ 38432946598 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	44593247290363030316925624895490083187412833119223555248796739131790682132274	107	UVM_INFO @ 163975840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	40233069741021118406814501556190684767557664045635567400330347675762725524818	107	UVM_INFO @ 289703957 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	5191282333394339595464081904823813710450986306844094657689749224136591448919	107	UVM_INFO @ 137328939 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	1080459624063760786187195645553912674243035529476986233812837976608217292366	107	UVM_INFO @ 349777197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	107839448419222696284141340499992361119947191811223228804029975125041241339169	107	UVM_INFO @ 1169251233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	85639776127542509133232632353328526122173358211382212735034090864254195249845	107	UVM_INFO @ 50355484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	15113501346650717314350064775344507394170568192956673288360220179419249237625	107	UVM_INFO @ 236535635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	41983817143942575640638378025068372481737286234526242792579039378722758522834	107	UVM_INFO @ 51811125 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	8551603739007850629332886622832311134540322325760734402283233030839345376009	107	UVM_INFO @ 179475807 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				15 test runs
	rv_dm_hart_unavail	77626009292916468397620245691164464295960063620505755058144014179481215851196	87	UVM_INFO @ 114697499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	104311399339582252691993360236498405034651033303618677699408851592404335484515	91	UVM_INFO @ 1387599870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	50566408797428054154931165534358401915288768672088995731304185161797169839171	87	UVM_INFO @ 92052114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	49552513229287564438689096884569348395232307400413285562826292064597153919981	88	UVM_INFO @ 226619336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	68045464603932609073098788352125054503402790370818419332794807883278296198297	87	UVM_INFO @ 195507469 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	19190401926894599780300803057599432599441151103764574928821006979031712146324	87	UVM_INFO @ 89549440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	92514377305238075254344417265318882973699214180796586957774450745339769833005	88	UVM_INFO @ 186157825 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	48195964312544371078215178647467719173636975730247860515167196494308556448597	93	UVM_INFO @ 1522110953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	14279214184573391107465276251683921851729506122389518815702677560382122245371	87	UVM_INFO @ 118302976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	94190335136671093257708425598828025148223187009047157476271010338786009632978	112	UVM_INFO @ 612221812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	15888113705223444472193111930876049842641408868501780161530294886617093838931	93	UVM_INFO @ 528393785 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	98331413997845275781197979300726123145093385376860726658648387897592891427885	92	UVM_INFO @ 597868407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	97357725991339899092899766926790312172514266662649197439304093534006316442459	91	UVM_INFO @ 143938877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	104518439103028395006058801897942558451183633641550636853659381197886211836564	88	UVM_INFO @ 41293982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	78177447622826109183590336534974216182533808722953394122954726809543593337541	88	UVM_INFO @ 200800464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				14 test runs
	rv_dm_mem_tl_access_resuming	27368506816675452373161860530302503692220683332098480078191750714464282978070	87	UVM_INFO @ 158441385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	59817663908983774140887163250694056006174948641679202850762648544107172640012	87	UVM_INFO @ 185616708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	49079764087668082672407861167711038897596705705398924959972719864426767074847	88	UVM_INFO @ 160248275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66219454312780153621729363023293179712784988959522453447834068104327624467874	117	UVM_INFO @ 3158873841 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	65688130919102365439926009591169272991054131117852427999055734534110095492837	127	UVM_INFO @ 1665545094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	10592766436987126335550887093512184669152794232983787801530514975305331361771	89	UVM_INFO @ 305193730 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	80156631385957342860587206153822647625825488680002352040853631671979861055504	97	UVM_INFO @ 4016948105 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	89150836373216153600310827890149184825653579150578428955990734211087852819458	89	UVM_INFO @ 900387089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	84864854227326734809524226559336182077599342796220754879667749828609552178730	132	UVM_INFO @ 2750140743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	95439741523544664858309566803661654563632911210128165083244138822504670457666	99	UVM_INFO @ 801929865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	21473350110654995323165196143697982557467083884216307035313583041517630913363	107	UVM_INFO @ 1957674440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	62972757876925364359252897321811780906771726960339159359864839169133048059495	91	UVM_INFO @ 151448300 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	18407182211629481370070129363923950426875965946843425412210583239934334985685	90	UVM_INFO @ 659322792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	76175899850989711182541660766057178798417767174055361672348630320056181865261	107	UVM_INFO @ 1757494625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				7 test runs
	rv_dm_jtag_dmi_debug_disabled	9364212081376362949824113017137968896406874651513449518643025692795680683112	87	UVM_INFO @ 318527764 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	92529464045039873032131543126335969908838938936359550678800997634904476439794	87	UVM_INFO @ 511675763 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	26079945086503501468983096160390148238944699120880871345238591157622841093256	93	UVM_INFO @ 2323482400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	62976454039871126108094165541150520260122538275431558224914377830593497161012	88	UVM_INFO @ 166293526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	31611438587623596620251390693717724263505135701193618955409111280873976464504	91	UVM_INFO @ 2403842067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	7631826654024100688855008626061413673737018146573715952106992800900894210052	112	UVM_INFO @ 699177399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	23291948727192339964676309660591098418152964553673669908563243884944808853483	94	UVM_INFO @ 3836495167 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				4 test runs
	rv_dm_scanmode	101504541925148305101937908014309141998318588893631125840433185753552522561643	87	UVM_INFO @ 300000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	45834189046631662425687657306908584622339174724063627486220538181451540811167	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	6687578335114379982404652894489781086819734157331419615756213314541024364900	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	26425375091367102377176737802478500228222651804039673850490639723773379146485	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				4 test runs
	rv_dm_buffered_enable	29128289339719342611073125813959376403691442641406423717092385202733818858074	93	UVM_INFO @ 592057633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	20385641047625226870274420119915638763917592825589140383746958219646074142095	89	UVM_INFO @ 223114384 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	4163038871063516468784711608246071021162011587828464570192615352267463870021	91	UVM_INFO @ 370826441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_buffered_enable	100167260112737947561862901858821955816754243810082632340411509628604407532800	93	UVM_INFO @ 480647312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done)				4 test runs
	rv_dm_stress_all_with_rand_reset	6142608216169481789729132891639149610320546001992056221000388021772151877321	122	UVM_INFO @ 4757400283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	81448309360550493106794465993785016945747379906398767334157352831602758010816	105	UVM_INFO @ 973043595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	99804274317876277348397999127018098917137566053748413143741040116624827784994	107	UVM_INFO @ 749079670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	24564814817111756618538869078304975116191735044256919145364758685884368839879	103	UVM_INFO @ 2383346052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [rv_dm_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				3 test runs
	rv_dm_sec_cm	43266620980520997208722548086690029048501509069996969757041073075953823346010	126	UVM_INFO @ 1553702039 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tl_intg_err	66730289437614247283712247765114475366384310402975281432547395452163533096147	248	UVM_INFO @ 4143700987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_tl_intg_err	92506751401202204483754347476623823349098159806685057627542271752437516658611	127	UVM_INFO @ 614357891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				2 test runs
	rv_dm_stress_all	79374968940251263386230734171417529751868144681050665807482984945016432078286	None
	rv_dm_stress_all	83314445294964619051332573319057980196347394127697528474692488374558523483811	None
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23871) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	84801746975974137318409580952501211000404181007858238322008214865980973505936	87	). UVM_INFO @ 15706247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23866) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	15741502058423640916465191219314988824400133477079431060892507349381576413057	87	). UVM_INFO @ 83334868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---