Simulation Results: rv_timer

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 90.45 %
  • assert
  • 97.47 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
57.50%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 312.196us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 54.730us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 15.782us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 4.000s 89.777us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 2.000s 61.658us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 1.000s 20.426us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 15.782us 5 5 100.00
rv_timer_csr_aliasing 2.000s 61.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 8.000s 4815.860us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 4.000s 1833.448us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 287.000s 804256.643us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 287.000s 804256.643us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 13.000s 7742.793us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 27.895us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 22.149us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 4.000s 196.894us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 4.000s 196.894us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 54.730us 1 1 100.00
rv_timer_csr_rw 2.000s 15.782us 5 5 100.00
rv_timer_csr_aliasing 2.000s 61.658us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 105.000us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 54.730us 1 1 100.00
rv_timer_csr_rw 2.000s 15.782us 5 5 100.00
rv_timer_csr_aliasing 2.000s 61.658us 1 1 100.00
rv_timer_same_csr_outstanding 2.000s 105.000us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 130.441us 5 5 100.00
rv_timer_tl_intg_err 2.000s 269.762us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 269.762us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 3.000s 1027.039us 2 10 20.00
max_value 1 10 10.00
rv_timer_max 2.000s 46.380us 1 10 10.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 62.000s 16961.129us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 42158829362445506079505966111767550511680261059507331617395321449391368688411 84
UVM_INFO @ 46379901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 57071473428094494598685005491635924006683231646894485518369541532996476351308 84
UVM_INFO @ 43211722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 104124606387434629543715596918145996609850346168433459925677795057564465923980 84
UVM_INFO @ 54708552 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 82680599974838757157926436038964650706683706916952840266896103383642859543027 84
UVM_INFO @ 87780769 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 38048960019062390513616849691833298802225276401670956550141804893981765603563 84
UVM_INFO @ 43763475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 23669661385113552402892172052558471333340545027836760699741113568361499262356 85
UVM_INFO @ 184469063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 35956934102630505201791571637483262701433399654363235903278983062634927199262 85
UVM_INFO @ 177713621 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 77597320656570018041663421623559647598597983104818897517522775837384296532936 86
UVM_INFO @ 195637880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 19422483118465520388410649284233174718937335293087501390372390396576575541739 84
UVM_INFO @ 178638842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 8 test runs
rv_timer_min 5859354475221633154016421389479938711791781818512240138087282418056526573821 85
UVM_INFO @ 56379694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 16210141228202919634547208206958852760338445490217680865086706381350758522719 84
UVM_INFO @ 64209947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 55024585902434829204714446979035930206965583733598266971332129490049204815547 85
UVM_INFO @ 127320216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 110665545100829465534248678332776470766427327283372964718370979127467278515639 84
UVM_INFO @ 400064633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 72573257281709275894359189591130948198312596858227780540720746668079185892790 87
UVM_INFO @ 90863615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 52053235731810027642213944074567469602878433543121123327404009158886110865542 84
UVM_INFO @ 68514077 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 102347499555042491555617768725499510519341932479663337357240004494187242015847 85
UVM_INFO @ 227839968 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 108002450467222015969229400447036963539754618571683966802762309615352235492215 85
UVM_INFO @ 1027038501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---