Simulation Results: spi_host

 
04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.82 %
  • code
  • 91.30 %
  • assert
  • 96.41 %
  • func
  • 90.76 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
99.45%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 70.000s 2414.427us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 40.087us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 20.867us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 186.340us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 23.403us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 68.044us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 20.867us 5 5 100.00
spi_host_csr_aliasing 1.000s 23.403us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 37.067us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 71.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 78.514us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 4.000s 292.854us 10 10 100.00
spi_host_error_cmd 2.000s 17.781us 10 10 100.00
spi_host_event 760.000s 60634.593us 10 10 100.00
clock_rate 9 10 90.00
spi_host_speed 20.000s 10057.703us 9 10 90.00
speed 9 10 90.00
spi_host_speed 20.000s 10057.703us 9 10 90.00
chip_select_timing 9 10 90.00
spi_host_speed 20.000s 10057.703us 9 10 90.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 577.000s 44109.487us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 23.000s 3247.561us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 243.049us 10 10 100.00
cpol_cpha 9 10 90.00
spi_host_speed 20.000s 10057.703us 9 10 90.00
full_cycle 9 10 90.00
spi_host_speed 20.000s 10057.703us 9 10 90.00
duplex 10 10 100.00
spi_host_smoke 70.000s 2414.427us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 70.000s 2414.427us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 80.000s 9744.838us 10 10 100.00
spien 10 10 100.00
spi_host_spien 9.000s 1857.805us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 1848.000s 350555.315us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 27.000s 2999.307us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 4.000s 292.854us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 25.087us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 19.285us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 3.000s 100.229us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 3.000s 100.229us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 40.087us 1 1 100.00
spi_host_csr_rw 2.000s 20.867us 5 5 100.00
spi_host_csr_aliasing 1.000s 23.403us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 80.476us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 40.087us 1 1 100.00
spi_host_csr_rw 2.000s 20.867us 5 5 100.00
spi_host_csr_aliasing 1.000s 23.403us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 80.476us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 2.000s 59.753us 25 25 100.00
spi_host_sec_cm 2.000s 269.353us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 2.000s 59.753us 25 25 100.00

Error Messages

   Test seed line log context
UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* 1 test run
spi_host_speed 26539403301706309593547292456047826599199600764662826993470455861305753446588 289
UVM_INFO @ 10057702571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---