| V1 |
|
97.30% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2660.377us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 51.221us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 18.864us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 3.000s | 60.908us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 56.790us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 4 | 5 | 80.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 19.000s | 10002.400us | 4 | 5 | 80.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 18.864us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 56.790us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 328.000s | 92781.053us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 122.000s | 10938.488us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 90.000s | 121469.448us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 297.000s | 7063.487us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 234.000s | 126516.182us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 82.000s | 42908.610us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 64.000s | 13854.580us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 43.000s | 7049.340us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 7.000s | 700.442us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 433.000s | 102177.351us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 7.000s | 1417.840us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 12.000s | 2657.040us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 8.000s | 13387.269us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 27.000s | 3140.034us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 4.000s | 1129.886us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2660.377us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 7.000s | 700.442us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 82.000s | 42908.610us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 537.000s | 200326.331us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 20.900us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 749.872us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 749.872us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 51.221us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 18.864us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 56.790us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 84.289us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 51.221us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 18.864us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 56.790us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 84.289us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 37.000s | 7255.259us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 702.730us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 4.000s | 281.065us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 702.730us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 4.000s | 281.065us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 27.000s | 3140.034us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 27.000s | 3140.034us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 18.864us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 43.000s | 7049.340us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 43.000s | 7049.340us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 43.000s | 7049.340us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 64.000s | 13854.580us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 37.000s | 7255.259us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2660.377us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2660.377us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 43.000s | 7049.340us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 702.730us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 64.000s | 13854.580us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 702.730us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 702.730us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 8.000s | 2660.377us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 702.730us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 56.000s | 30143.698us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 106329043629590608088800889598700061963621622076480960318665036907737444169482 | None | ||
| sram_ctrl_mubi_enc_err | 33676944459250621805321779788492680387644417062430310829559123739795567483419 | None | ||
| sram_ctrl_readback_err | 4163281388500031561605426905541823122821598054769409820821405921045859025380 | None | ||
| sram_ctrl_mubi_enc_err | 60165054313568100320939883596397430498416033203534088341130756368220516282818 | None | ||
| sram_ctrl_readback_err | 65397132412275620350475866719023467601685304453499850960927546614559703467934 | None | ||
| sram_ctrl_mubi_enc_err | 41958091336372293043893655436879574239927197790868989108843170854471111807704 | None | ||
| sram_ctrl_readback_err | 39496201205167439638349922044167232966250743522430216840985297409859637676533 | None | ||
| sram_ctrl_mubi_enc_err | 12145394807812433626323976007079622529090099086620296711555000476539730928216 | None | ||
| sram_ctrl_readback_err | 59791967717261048543186530608721866884546798152836751842299295961961773801258 | None | ||
| sram_ctrl_mubi_enc_err | 74968648005463390549936199125381521703416094969425517045418011336250237174056 | None | ||
| sram_ctrl_readback_err | 58635115780006514227673485159601187568562991442880590904442799136881444731573 | None | ||
| sram_ctrl_mubi_enc_err | 108939842689502844528406909579245956791808354397036229773911723969924645421505 | None | ||
| sram_ctrl_readback_err | 64422612075010578248412259680864172610519549315186820463453155028527169134984 | None | ||
| sram_ctrl_mubi_enc_err | 114421589974220203219824616498278682954166464909195483831580036590486624881958 | None | ||
| sram_ctrl_readback_err | 74087724913097935305766233309756137970274154107283975539084292335546336054988 | None | ||
| sram_ctrl_mubi_enc_err | 97754929217448907350365030985319775336602107974345924402303481902407698602846 | None | ||
| UVM_FATAL (sram_ctrl_base_vseq.sv:177) [sram_ctrl_common_vseq] Timed out waiting for initialization done | 1 test run | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 93322004066090291129627210159918712190592060478900340730004671421237305864597 | 85 |
UVM_INFO @ 10002399661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
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