| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 12.000s | 342.044us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 31.156us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 39.246us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 3.000s | 221.969us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 16.954us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 2.000s | 391.144us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 39.246us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 16.954us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 12.000s | 2551.679us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 7.000s | 2513.683us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 13.000s | 2901.146us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 208.000s | 3463.349us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 9.000s | 1923.397us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 22.000s | 2949.085us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 1366.195us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 993.566us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 212.800us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 370.000s | 92264.761us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 137.934us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 17.000s | 47.941us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 11.000s | 252.855us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 13.000s | 2725.392us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 203.109us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 12.000s | 342.044us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 3.000s | 212.800us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 22.000s | 2949.085us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 91.000s | 5473.641us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 2.000s | 55.399us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 10.000s | 65.919us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 10.000s | 65.919us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 31.156us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 39.246us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 16.954us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 33.336us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 1.000s | 31.156us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 39.246us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 16.954us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 33.336us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 1514.385us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 4.000s | 163.985us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 6.000s | 399.880us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 4.000s | 163.985us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 6.000s | 399.880us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 13.000s | 2725.392us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 13.000s | 2725.392us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 39.246us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 993.566us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 993.566us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 993.566us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 1366.195us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3600.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 5.000s | 1514.385us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3600.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 12.000s | 342.044us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 12.000s | 342.044us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 993.566us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 4.000s | 163.985us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 8.000s | 1366.195us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 4.000s | 163.985us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 4.000s | 163.985us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 12.000s | 342.044us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 4.000s | 163.985us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 57.000s | 3062.061us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 109364248412722480045120377243524014079902620480365151733321308522715230546995 | None | ||
| sram_ctrl_mubi_enc_err | 47061139690133593221890005818212234323755587521448566356409084345168161606015 | None | ||
| sram_ctrl_readback_err | 72043021997786256221554700669303064852287562552519688603523820594845122765833 | None | ||
| sram_ctrl_mubi_enc_err | 40418878962587958247883461112329857642125080938261462816200033276046029270196 | None | ||
| sram_ctrl_readback_err | 112061327624521680789798106454058594074883038975245982517546089653727684302230 | None | ||
| sram_ctrl_mubi_enc_err | 2153267960203730192358387299037433784623867048711957376803239840343618820728 | None | ||
| sram_ctrl_readback_err | 90541355723589493877444785459219179958750703921211307115851973533091105847393 | None | ||
| sram_ctrl_mubi_enc_err | 11574320872470845745930113520702564672999806874453088469519295663791573532308 | None | ||
| sram_ctrl_readback_err | 61749367820745174105543930705398407663377548267764428792936396232529066302365 | None | ||
| sram_ctrl_mubi_enc_err | 105175715304301366518931611038451286467226264003365297354804979479042641352760 | None | ||
| sram_ctrl_readback_err | 43469029032660858712709191550713021137536573270163318651740254182437723868037 | None | ||
| sram_ctrl_mubi_enc_err | 96634443704966637506520142199916518197369094749887103561040909734724847562057 | None | ||
| sram_ctrl_readback_err | 54677405863625424249473916668400200406500942577853377002079248534060685373205 | None | ||
| sram_ctrl_mubi_enc_err | 19517846215899319011127537258518770266225186219053874049403317956099218848926 | None | ||
| sram_ctrl_readback_err | 111225510054423875002582756364386719050344904954586283249910515972522224469700 | None | ||
| sram_ctrl_mubi_enc_err | 87178598464197176106452598277107814865468768137027430942726433658877319089509 | None | ||