Simulation Results

Simulation Results: uart

04/09/2026 15:01:37 DVSim: v1.49.0 sha: 02ae8da json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
94.09 %

code
92.73 %

assert
98.85 %

func
90.69 %

block
99.08 %

line
99.52 %

branch
98.34 %

toggle
73.08 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		96.47%
V2S		100.00%
V3		80.00%

23/23 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	uart_smoke	23.000s	6079.402us	10	10	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	1.000s	18.490us	1	1	100.00
csr_rw				5	5	100.00
	uart_csr_rw	2.000s	45.162us	5	5	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	3.000s	83.953us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	1.000s	38.863us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	uart_csr_mem_rw_with_rand_reset	2.000s	141.479us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	uart_csr_rw	2.000s	45.162us	5	5	100.00
	uart_csr_aliasing	1.000s	38.863us	1	1	100.00

383/397 passed

96.47 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				10	10	100.00
	uart_tx_rx	161.000s	84581.585us	10	10	100.00
parity				20	20	100.00
	uart_smoke	23.000s	6079.402us	10	10	100.00
	uart_tx_rx	161.000s	84581.585us	10	10	100.00
parity_error				20	20	100.00
	uart_intr	99.000s	48561.676us	10	10	100.00
	uart_rx_parity_err	334.000s	147564.315us	10	10	100.00
watermark				20	20	100.00
	uart_tx_rx	161.000s	84581.585us	10	10	100.00
	uart_intr	99.000s	48561.676us	10	10	100.00
fifo_full				10	10	100.00
	uart_fifo_full	266.000s	178324.610us	10	10	100.00
fifo_overflow				9	10	90.00
	uart_fifo_overflow	318.000s	171138.370us	9	10	90.00
fifo_reset				199	200	99.50
	uart_fifo_reset	363.000s	153505.244us	199	200	99.50
rx_frame_err				10	10	100.00
	uart_intr	99.000s	48561.676us	10	10	100.00
rx_break_err				10	10	100.00
	uart_intr	99.000s	48561.676us	10	10	100.00
rx_timeout				10	10	100.00
	uart_intr	99.000s	48561.676us	10	10	100.00
perf				10	10	100.00
	uart_perf	666.000s	24696.335us	10	10	100.00
sys_loopback				10	10	100.00
	uart_loopback	24.000s	10262.282us	10	10	100.00
line_loopback				10	10	100.00
	uart_loopback	24.000s	10262.282us	10	10	100.00
rx_noise_filter				1	10	10.00
	uart_noise_filter	77.000s	57595.319us	1	10	10.00
rx_start_bit_filter				10	10	100.00
	uart_rx_start_bit_filter	87.000s	47072.578us	10	10	100.00
tx_overide				10	10	100.00
	uart_tx_ovrd	21.000s	8100.228us	10	10	100.00
rx_oversample				10	10	100.00
	uart_rx_oversample	44.000s	6320.415us	10	10	100.00
long_b2b_transfer				10	10	100.00
	uart_long_xfer_wo_dly	870.000s	87818.722us	10	10	100.00
stress_all				7	10	70.00
	uart_stress_all	977.000s	293321.760us	7	10	70.00
alert_test				10	10	100.00
	uart_alert_test	1.000s	44.099us	10	10	100.00
intr_test				10	10	100.00
	uart_intr_test	2.000s	13.164us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	uart_tl_errors	3.000s	82.635us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	uart_tl_errors	3.000s	82.635us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	uart_csr_hw_reset	1.000s	18.490us	1	1	100.00
	uart_csr_rw	2.000s	45.162us	5	5	100.00
	uart_csr_aliasing	1.000s	38.863us	1	1	100.00
	uart_same_csr_outstanding	2.000s	22.763us	5	5	100.00
tl_d_partial_access				12	12	100.00
	uart_csr_hw_reset	1.000s	18.490us	1	1	100.00
	uart_csr_rw	2.000s	45.162us	5	5	100.00
	uart_csr_aliasing	1.000s	38.863us	1	1	100.00
	uart_same_csr_outstanding	2.000s	22.763us	5	5	100.00

V2S

30/30 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	uart_sec_cm	2.000s	263.317us	5	5	100.00
	uart_tl_intg_err	3.000s	90.309us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	uart_tl_intg_err	3.000s	90.309us	25	25	100.00

16/20 passed

80.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				16	20	80.00
	uart_stress_all_with_rand_reset	71.000s	5891.814us	16	20	80.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: , clk_pulses:				8 test runs
	uart_noise_filter	42765182676875574401572186223088474381873282302794194345537399470666758658238	85	UVM_ERROR @ 2018667865 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2018959534 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (87 [0x57] vs 253 [0xfd]) reg name: uart_reg_block.rdata UVM_ERROR @ 2019042868 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2019126202 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (87 [0x57] vs 255 [0xff]) reg name: uart_reg_block.rdata
	uart_stress_all	109411614615528961059810202791017067101608758533362180045974759006834137357985	106	UVM_ERROR @ 23794942291 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 23795215021 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata UVM_ERROR @ 24054535796 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 24058126741 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	7579759774063901719569611553888295608374657453280724571710026518319373443628	84	UVM_ERROR @ 11051246258 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 11053046258 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 14069846258 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 12, clk_pulses: 0 UVM_ERROR @ 14070246258 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	29109730124906280666287707347612382994707051258292946441768159179331415289973	83	UVM_ERROR @ 283611756 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 283652572 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 398957772 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 7, clk_pulses: 0 UVM_ERROR @ 398998588 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	46878508436744356924227912714435923288635089331303741891458690061550878470301	89	UVM_ERROR @ 39924139054 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 39924179054 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (79 [0x4f] vs 255 [0xff]) reg name: uart_reg_block.rdata UVM_ERROR @ 39924259054 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 39924299054 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (79 [0x4f] vs 255 [0xff]) reg name: uart_reg_block.rdata
	uart_stress_all	74991219469350998421565327477591086242511203908396351554532180782895939661269	84	UVM_ERROR @ 1100580291 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 1100780291 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 127 [0x7f]) reg name: uart_reg_block.rdata UVM_ERROR @ 1768100291 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6, clk_pulses: 0 UVM_ERROR @ 1768180291 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
	uart_noise_filter	98911112482320261749697291518481377450299143035109815922513802885981875026444	84	UVM_ERROR @ 4938410077 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 4938910081 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 117 [0x75]) reg name: uart_reg_block.rdata UVM_ERROR @ 4938993415 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 4939410085 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 223 [0xdf]) reg name: uart_reg_block.rdata
	uart_stress_all_with_rand_reset	75731682433158518090190401388017709671979728608374123274559639591161394969460	211	UVM_ERROR @ 25342638704 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 25342705371 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 117 [0x75]) reg name: uart_reg_block.rdata UVM_INFO @ 25431639149 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 2/334 UVM_ERROR @ 25468372666 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *				5 test runs
	uart_noise_filter	69602287287778344805211609500335995736203216683383130774220449588225309993289	83	UVM_ERROR @ 25043184 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 26876532 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 28098764 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 29320996 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_stress_all_with_rand_reset	46867984190456980514985010476739337632723151934329557394526998449402486260214	86	UVM_ERROR @ 31219559 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 32019563 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 32552899 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 32952901 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
	uart_noise_filter	41852836149744076071200845287432577770231374700291997071540671229264340585844	85	UVM_ERROR @ 2262937567 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 2897771153 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 2, clk_pulses: 0 UVM_ERROR @ 2897792205 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 2897897465 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (121 [0x79] vs 255 [0xff]) reg name: uart_reg_block.rdata
	uart_stress_all	42186322926452819643207797312524290862910563174448932886945808192019158967759	139	UVM_ERROR @ 301236541512 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 301286246936 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 301286246936 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 301364404982 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
	uart_stress_all_with_rand_reset	33601752048477679187784721304260961093648987114501917768408951985163376866516	100	UVM_ERROR @ 299137041 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 320470417 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 340470457 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 345137133 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *				2 test runs
	uart_noise_filter	29304483374304282014258431198718405567316462531481617502467336795898447476546	87	UVM_ERROR @ 57364272444 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 13, clk_pulses: 0 UVM_ERROR @ 57364421383 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (8 [0x8] vs 231 [0xe7]) reg name: uart_reg_block.rdata UVM_ERROR @ 57364463937 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty UVM_ERROR @ 57364570322 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (8 [0x8] vs 253 [0xfd]) reg name: uart_reg_block.rdata
	uart_noise_filter	57905874545271579529110755357402631335209414897511073422398121071051281353018	83	UVM_ERROR @ 751522238 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 751522238 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_ERROR @ 1098664748 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 3, clk_pulses: 0 UVM_ERROR @ 1098807605 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (82 [0x52] vs 239 [0xef]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:445) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [] vs [*]) Interrupt_pin: TxEmpty				2 test runs
	uart_fifo_overflow	30728012818009791031578391519067279493920313768317929346289076371351791469142	83	UVM_INFO @ 424482203 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 1/10 UVM_INFO @ 437622369 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 2/10 UVM_INFO @ 2353699439 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 3/10 UVM_INFO @ 6906304579 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_overflow_vseq] finished run 4/10
	uart_fifo_reset	78598255018753886764338308675160465070324731005092693263337548731352097035666	88	UVM_INFO @ 140429676912 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 6/8 UVM_INFO @ 141289629101 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 7/8 UVM_INFO @ 142244432334 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_fifo_reset_vseq] finished run 8/8 UVM_INFO @ 158001196912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [] vs [*]) Interrupt: RxParityErr				1 test run
	uart_stress_all_with_rand_reset	108258744295024386392056544048941843488255088343907212799319665740837565506625	190	UVM_ERROR @ 1918620185 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr UVM_INFO @ 1936120185 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 3/441 UVM_ERROR @ 1946610185 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0 UVM_ERROR @ 1946620185 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty