Simulation Results: ac_range_check

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.31 %
  • code
  • 93.56 %
  • assert
  • 97.75 %
  • func
  • 58.63 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.52 %
Validation stages
V1
94.34%
V2
98.86%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 18 20 90.00
ac_range_check_smoke 46.000s 1625.015us 18 20 90.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 62.000s 11557.343us 19 20 95.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 3.000s 42.324us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 3.000s 140.620us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 31.000s 1764.545us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 4.000s 496.420us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 3.000s 94.275us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 3.000s 140.620us 5 5 100.00
ac_range_check_csr_aliasing 4.000s 496.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 4.000s 117.102us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 26.000s 1793.309us 1 1 100.00
stress_all 9 10 90.00
ac_range_check_stress_all 337.000s 52225.754us 9 10 90.00
alert_test 10 10 100.00
ac_range_check_alert_test 28.000s 15.674us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 2.000s 51.365us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 5.000s 789.688us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 5.000s 789.688us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 3.000s 42.324us 1 1 100.00
ac_range_check_csr_rw 3.000s 140.620us 5 5 100.00
ac_range_check_csr_aliasing 4.000s 496.420us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 193.989us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 3.000s 42.324us 1 1 100.00
ac_range_check_csr_rw 3.000s 140.620us 5 5 100.00
ac_range_check_csr_aliasing 4.000s 496.420us 1 1 100.00
ac_range_check_same_csr_outstanding 6.000s 193.989us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 21.000s 3921.098us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 21.000s 3921.098us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 21.000s 3921.098us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 21.000s 3921.098us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 121.000s 4796.507us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 13.822us 5 5 100.00
ac_range_check_tl_intg_err 13.000s 1634.788us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 10 10 100.00
ac_range_check_stress_all_with_rand_reset 389.000s 12151.117us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 38.000s 6162.633us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 4 test runs
ac_range_check_smoke 22734831551486143289517406361325858157320536943247967162467956315803228222168 4254
UVM_INFO @ 1525192472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_stress_all 67058579980797854100017812743918264492339585472154866532651404646643480055250 17260
UVM_INFO @ 13606190216 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke 66983439379380994853529724372191274367595843567440927485717371519527909234461 4414
UVM_INFO @ 6451297702 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
ac_range_check_smoke_racl 42820750019779879984816826723990420027944266876975647834040798570528876233747 4084
UVM_INFO @ 2901249897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---