Simulation Results

Simulation Results: aes/gcm_masked

11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
96.98 %

code
98.04 %

assert
98.57 %

func
94.34 %

block
98.08 %

line
99.06 %

branch
95.04 %

toggle
98.05 %

FSM
100.00 %

Validation stages

V1		100.00%
V2		98.12%
V2S		91.97%
V3		0.00%

24/24 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	aes_wake_up	7.000s	253.927us	1	1	100.00
smoke				10	10	100.00
	aes_smoke	9.000s	706.824us	10	10	100.00
csr_hw_reset				1	1	100.00
	aes_csr_hw_reset	2.000s	63.097us	1	1	100.00
csr_rw				5	5	100.00
	aes_csr_rw	2.000s	75.724us	5	5	100.00
csr_bit_bash				1	1	100.00
	aes_csr_bit_bash	8.000s	483.799us	1	1	100.00
csr_aliasing				1	1	100.00
	aes_csr_aliasing	3.000s	65.562us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	aes_csr_mem_rw_with_rand_reset	2.000s	88.758us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	aes_csr_rw	2.000s	75.724us	5	5	100.00
	aes_csr_aliasing	3.000s	65.562us	1	1	100.00

313/319 passed

98.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
algorithm				70	70	100.00
	aes_smoke	9.000s	706.824us	10	10	100.00
	aes_config_error	37.000s	3071.304us	50	50	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
key_length				70	70	100.00
	aes_smoke	9.000s	706.824us	10	10	100.00
	aes_config_error	37.000s	3071.304us	50	50	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
back2back				35	35	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
	aes_b2b	26.000s	725.811us	25	25	100.00
backpressure				10	10	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
multi_message				90	95	94.74
	aes_smoke	9.000s	706.824us	10	10	100.00
	aes_config_error	37.000s	3071.304us	50	50	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
	aes_alert_reset	3606.000s	0.000us	20	25	80.00
failure_test				80	85	94.12
	aes_man_cfg_err	4.000s	100.168us	10	10	100.00
	aes_config_error	37.000s	3071.304us	50	50	100.00
	aes_alert_reset	3606.000s	0.000us	20	25	80.00
trigger_clear_test				10	10	100.00
	aes_clear	10.000s	568.912us	10	10	100.00
nist_test_vectors				1	1	100.00
	aes_nist_vectors	13.000s	2335.767us	1	1	100.00
nist_test_vectors_gcm				1	1	100.00
	aes_nist_vectors_gcm	14.000s	698.227us	1	1	100.00
reset_recovery				20	25	80.00
	aes_alert_reset	3606.000s	0.000us	20	25	80.00
stress				10	10	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
sideload				20	20	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
	aes_sideload	6.000s	187.193us	10	10	100.00
deinitialization				10	10	100.00
	aes_deinit	9.000s	322.889us	10	10	100.00
stress_all				9	10	90.00
	aes_stress_all	59.000s	5988.492us	9	10	90.00
gcm_save_and_restore				100	100	100.00
	aes_gcm_save_restore	13.000s	4067.640us	100	100	100.00
alert_test				10	10	100.00
	aes_alert_test	6.000s	87.431us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	aes_tl_errors	4.000s	1908.252us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	aes_tl_errors	4.000s	1908.252us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	aes_csr_hw_reset	2.000s	63.097us	1	1	100.00
	aes_csr_rw	2.000s	75.724us	5	5	100.00
	aes_csr_aliasing	3.000s	65.562us	1	1	100.00
	aes_same_csr_outstanding	3.000s	132.333us	5	5	100.00
tl_d_partial_access				12	12	100.00
	aes_csr_hw_reset	2.000s	63.097us	1	1	100.00
	aes_csr_rw	2.000s	75.724us	5	5	100.00
	aes_csr_aliasing	3.000s	65.562us	1	1	100.00
	aes_same_csr_outstanding	3.000s	132.333us	5	5	100.00

V2S

1076/1170 passed

91.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
reseeding				9	10	90.00
	aes_reseed	9.000s	329.476us	9	10	90.00
fault_inject				579	660	87.73
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_cipher_fi	61.000s	0.000us	312	350	89.14
shadow_reg_update_error				20	20	100.00
	aes_shadow_reg_errors	7.000s	102.265us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	aes_shadow_reg_errors	7.000s	102.265us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	aes_shadow_reg_errors	7.000s	102.265us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	aes_shadow_reg_errors	7.000s	102.265us	20	20	100.00
shadow_reg_update_error_with_csr_rw				19	20	95.00
	aes_shadow_reg_errors_with_csr_rw	5.000s	2659.498us	19	20	95.00
tl_intg_err				29	30	96.67
	aes_sec_cm	16.000s	1515.836us	5	5	100.00
	aes_tl_intg_err	4.000s	363.930us	24	25	96.00
sec_cm_bus_integrity				24	25	96.00
	aes_tl_intg_err	4.000s	363.930us	24	25	96.00
sec_cm_lc_escalate_en_intersig_mubi				20	25	80.00
	aes_alert_reset	3606.000s	0.000us	20	25	80.00
sec_cm_main_config_shadow				20	20	100.00
	aes_shadow_reg_errors	7.000s	102.265us	20	20	100.00
sec_cm_gcm_config_shadow				20	20	100.00
	aes_shadow_reg_errors	7.000s	102.265us	20	20	100.00
sec_cm_main_config_sparse				135	145	93.10
	aes_smoke	9.000s	706.824us	10	10	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
	aes_alert_reset	3606.000s	0.000us	20	25	80.00
	aes_core_fi	3601.000s	0.000us	95	100	95.00
sec_cm_gcm_config_sparse				255	260	98.08
	aes_gcm_save_restore	13.000s	4067.640us	100	100	100.00
	aes_config_error	37.000s	3071.304us	50	50	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
	aes_core_fi	3601.000s	0.000us	95	100	95.00
sec_cm_aux_config_shadow				20	20	100.00
	aes_shadow_reg_errors	7.000s	102.265us	20	20	100.00
sec_cm_aux_config_regwen				20	20	100.00
	aes_readability	3.000s	107.186us	10	10	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
sec_cm_key_sideload				20	20	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
	aes_sideload	6.000s	187.193us	10	10	100.00
sec_cm_key_sw_unreadable				10	10	100.00
	aes_readability	3.000s	107.186us	10	10	100.00
sec_cm_data_reg_sw_unreadable				10	10	100.00
	aes_readability	3.000s	107.186us	10	10	100.00
sec_cm_key_sec_wipe				10	10	100.00
	aes_readability	3.000s	107.186us	10	10	100.00
sec_cm_iv_config_sec_wipe				10	10	100.00
	aes_readability	3.000s	107.186us	10	10	100.00
sec_cm_data_reg_sec_wipe				10	10	100.00
	aes_readability	3.000s	107.186us	10	10	100.00
sec_cm_data_reg_key_sca				10	10	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
sec_cm_key_masking				10	10	100.00
	aes_stress	7.000s	1999.715us	10	10	100.00
sec_cm_main_fsm_sparse				0	10	0.00
	aes_fi	3609.000s	0.000us	0	10	0.00
sec_cm_main_fsm_redun				604	685	88.18
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_cipher_fi	61.000s	0.000us	312	350	89.14
	aes_ctr_fi	5.000s	69.288us	25	25	100.00
sec_cm_cipher_fsm_sparse				0	10	0.00
	aes_fi	3609.000s	0.000us	0	10	0.00
sec_cm_cipher_fsm_redun				579	660	87.73
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_cipher_fi	61.000s	0.000us	312	350	89.14
sec_cm_cipher_ctr_redun				312	350	89.14
	aes_cipher_fi	61.000s	0.000us	312	350	89.14
sec_cm_ctr_fsm_sparse				0	10	0.00
	aes_fi	3609.000s	0.000us	0	10	0.00
sec_cm_ctr_fsm_redun				292	335	87.16
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_ctr_fi	5.000s	69.288us	25	25	100.00
sec_cm_ghash_fsm_sparse				0	10	0.00
	aes_fi	3609.000s	0.000us	0	10	0.00
sec_cm_ctrl_sparse				604	685	88.18
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_cipher_fi	61.000s	0.000us	312	350	89.14
	aes_ctr_fi	5.000s	69.288us	25	25	100.00
sec_cm_main_fsm_global_esc				20	25	80.00
	aes_alert_reset	3606.000s	0.000us	20	25	80.00
sec_cm_main_fsm_local_esc				604	685	88.18
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_cipher_fi	61.000s	0.000us	312	350	89.14
	aes_ctr_fi	5.000s	69.288us	25	25	100.00
sec_cm_cipher_fsm_local_esc				604	685	88.18
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_cipher_fi	61.000s	0.000us	312	350	89.14
	aes_ctr_fi	5.000s	69.288us	25	25	100.00
sec_cm_ctr_fsm_local_esc				292	335	87.16
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_ctr_fi	5.000s	69.288us	25	25	100.00
sec_cm_ghash_fsm_local_esc				90	100	90.00
	aes_ghash_fi	5.000s	481.813us	90	90	100.00
	aes_fi	3609.000s	0.000us	0	10	0.00
sec_cm_data_reg_local_esc				579	660	87.73
	aes_fi	3609.000s	0.000us	0	10	0.00
	aes_control_fi	61.000s	0.000us	267	300	89.00
	aes_cipher_fi	61.000s	0.000us	312	350	89.14

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	aes_stress_all_with_rand_reset	15.000s	1001.908us	0	10	0.00

Error Messages

	Test	seed	line	log context
Job timed out after * minutes				46 test runs
	aes_alert_reset	115626993513729223399481533716055510120642559773050967924396407849939747537618	None
	aes_fi	81322287154728518634641770143331375369592512365716984669377674299808638523373	None
	aes_cipher_fi	26385833994879939596022010383105936285346074014078511462505353017284703444906	None
	aes_fi	73489165620107223892507938541960873813861105104357821257401814867877235805704	None
	aes_alert_reset	52036347676885661081689543457574765591924797267579987126450953164486585987190	None
	aes_alert_reset	69143956204735286441515495586703896327840905265886100364990388035377824196173	None
	aes_cipher_fi	21601710074787298351289654473974202586527348239789433292160099898671888014455	None
	aes_alert_reset	34133802065123035795256658710943598451882237182597189080506027367803525915899	None
	aes_control_fi	79142174582646732038112998349494760638293298362765159843791085190269051577261	None
	aes_control_fi	55042604215171445483394476171619614095001070536691822024619728644570733585176	None
	aes_core_fi	34008184745326840986350194845705075424232332544295846914979007691455865023106	None
	aes_control_fi	97981489712572842037896909596905994942085233516653640913769085386229113963842	None
	aes_cipher_fi	62031378454672784793991819505112012092257976958674321280868498204976914622131	None
	aes_cipher_fi	101470969591627395427716428162703027202842108304687781292962129382124799165345	None
	aes_control_fi	71741080169980229428684128482550382770926597868039521284940159049427790681065	None
	aes_control_fi	37007024436448714290890277138946625594473095066217874519462552495149953301862	None
	aes_cipher_fi	98554338178482229415068110423884378812372827015438092631306138781820346201778	None
	aes_control_fi	54235353082679599711991935588602678168374242095481952915985753721121921590213	None
	aes_control_fi	87200369222226998210043127416662227000653256777074360965738582311521579623433	None
	aes_control_fi	82827065782430809082397736879473783217721050975251075341668859078818467593883	None
	aes_control_fi	107964834776595409927390087387543278870686168565578758852924017138473857149739	None
	aes_cipher_fi	7832534571954519007205429221813524681183216721229695478769543203661648961426	None
	aes_control_fi	23485638874731397469251633826714174928212423273280928566284486233105178017598	None
	aes_cipher_fi	38277104700537121210577413387377902446228649049079795954328292904186978187669	None
	aes_control_fi	33470935059379032377514282033756701509571774277964077147964299427461799717989	None
	aes_control_fi	18420625262756217382152153279641198261453223803494964138204478699967741289326	None
	aes_cipher_fi	28399725047265362434366144729053526565844212678833987102770202163969736149475	None
	aes_cipher_fi	79023649228300757405549277462208910359200164598211080254966352962924137423877	None
	aes_control_fi	46722882337282252612116279269172334439329658154362688121964523550761383344651	None
	aes_control_fi	54674893738133278852476299480778012128529167235182757229671018077546140922386	None
	aes_cipher_fi	62032057140430889495736147582906652662533694461740300815340376129054574391343	None
	aes_control_fi	69446861932358067522344142549624163373742259979100322007427765783278115760202	None
	aes_control_fi	6581137485327022981925345514881120708357010300664460765426928737417766607338	None
	aes_control_fi	80256921618056320596791757436860556376784190025346384289338190343608396114036	None
	aes_cipher_fi	86220066233381371159785071946653106438042220072592314867814994231240209332352	None
	aes_control_fi	69395752282942497454299031576923048968618651474087866657071173725613553910194	None
	aes_cipher_fi	52627865575070484515296835244597596766244786840832955757573709099751263299711	None
	aes_control_fi	21336968639487270870670606812205353410395818193528032826528614129498895533492	None
	aes_cipher_fi	32066414114066564858180953473337691894751427494736965204513884886865917523201	None
	aes_cipher_fi	53451184707320579347081391075245068980280223923188871804154483478510992301878	None
	aes_cipher_fi	74805117145004053352007529950002167103073301194913006566875960741509153736830	None
	aes_cipher_fi	16685732462147123762644383753440106167347950588249000736134128374090661942197	None
	aes_cipher_fi	88831463121372719680330665194573666016159582046142259944652877488223210665659	None
	aes_cipher_fi	12485215709699258620511463456103267430763720081924948627625975622777309829777	None
	aes_cipher_fi	86411926045472139405755234126110890698848679828563550806420898760216958035364	None
	aes_cipher_fi	94517037638296764753577069431300629124740259209823089952309843057984062327524	None
UVM_FATAL (aes_cipher_fi_vseq.sv:62) [aes_cipher_fi_vseq] wait timeout occurred!				18 test runs
	aes_cipher_fi	15407766288897636120128385645445794738527326231625152012414131280743481388163	143	UVM_INFO @ 10024383885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	24309735686393452209021525215209186101701820855076625776012004479075262441795	155	UVM_INFO @ 10032176916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	54825703219936859653885711622509697966416812199634137118755391025587412172916	154	UVM_INFO @ 10057461326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	50679480049828542740141369699080873065693488626553666000618104958940392874586	145	UVM_INFO @ 10016864476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	32754840772815153751672557659679314541654384857319389732631654905174030050124	146	UVM_INFO @ 10030252663 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	46161278578870316882757069914700983121671688145990887870438447506381203442679	145	UVM_INFO @ 10081905231 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	103693077826383490193001903252025929933992146011641310643763449433763331336107	152	UVM_INFO @ 10017890789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	71513705483274411132291754910955107117338007766281474753690065644461881660146	148	UVM_INFO @ 10007765191 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	47950027669672491103093284153998700834635053051208293066491216083822395654443	150	UVM_INFO @ 10011592057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	36740925200580175054421695929424781712918513673406908397720444050331176482723	156	UVM_INFO @ 10011628419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	77137617135756683184938413299698935631051033985779488965182671301458652013054	145	UVM_INFO @ 10009664770 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	15881324311687557203495601819158232083912231474474150641028537924215450703740	147	UVM_INFO @ 10018172312 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	6708238121376575311982783945028353411955833099155973088293886846181528854957	155	UVM_INFO @ 10014078379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	20684868329516977058909194709260079715685845928152881105738098028968040119299	152	UVM_INFO @ 10043554582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	78710100120171894428858054353966763076006087352367667135212668647155409433837	145	UVM_INFO @ 10018852833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	33879090262025775365648391099107417624737004419626207032266119696537401730137	148	UVM_INFO @ 10015220673 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	106311284071524135950889372436436716346014808817960289212681672072926238086391	157	UVM_INFO @ 10010795369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_cipher_fi	8573669185516492998857839664048947862945588769851970773799547355239627280768	149	UVM_INFO @ 10027191197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred!				14 test runs
	aes_control_fi	55592285189033331675186712504053684820989429325036155741920622913792611680715	146	UVM_INFO @ 10017307494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	66837705733963112269549301800414309294511296642262619986311355661318383547065	144	UVM_INFO @ 10020372133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	46735792874167734195981346038907972663071404336666598687880187443922019848259	155	UVM_INFO @ 10034264196 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	93522897560654089365023337421153454822307113688543314543975701699686067129993	149	UVM_INFO @ 10047660766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	112579918257114857130832141481787225765865746146379880322250254866082941943557	155	UVM_INFO @ 10005507577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	106554531276553634154068091235521279335413520744840858478700165757138775940889	157	UVM_INFO @ 10011942408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	65908387068754526854439060085702393482737246734399575553162311950909364022943	142	UVM_INFO @ 10006480146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	39534284401572818520038514332347260381936950834599303460798810687260980296917	146	UVM_INFO @ 10071737571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	110717042116026531128194511049232241019176394279871364248250053995507319757447	148	UVM_INFO @ 10033323540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	83179136806022134581001191618482484811096934568954888159746504782584372072749	146	UVM_INFO @ 10008940000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	28106654072663692119691774421525663161960290934232354514435132417551783915792	155	UVM_INFO @ 10038700553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	42256040453173699630259705745384042642821659226395819406031842466782309800233	154	UVM_INFO @ 10067141889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	41320795020578416353300024971087345304995517974416400441366067959759319884513	149	UVM_INFO @ 10011228340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_control_fi	56960052896217503937946938736338307523469758537370590776343607469541948679052	151	UVM_INFO @ 10012470644 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:923) scoreboard [scoreboard]				7 test runs
	aes_fi	45835625058907498577063426267754297979998688303900965160786698323485464141593	7115	----\| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL ----\| Expected: 4 ----\| Seen: 3 ----\| Expected corrupted: 0
	aes_fi	85421090913750526136426278906343996481153197295487676186679017516615333822559	27856	----\| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL ----\| Expected: 5 ----\| Seen: 4 ----\| Expected corrupted: 0
	aes_fi	106275297897814740186457586478922547005070636994496779064593425583013344452733	10052	----\| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL ----\| Expected: 4 ----\| Seen: 3 ----\| Expected corrupted: 0
	aes_fi	88401751585080248781504309870717819834758081637665357861014742210604576974442	20242	----\| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL ----\| Expected: 6 ----\| Seen: 4 ----\| Expected corrupted: 0
	aes_fi	61302640657332693906119950917266069267388130706079494364089026481157462867281	24621	----\| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL ----\| Expected: 6 ----\| Seen: 5 ----\| Expected corrupted: 0
	aes_fi	47683588690976639146740601205848188463531925412951331381742682248393347175216	257218	----\| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL ----\| Expected: 6 ----\| Seen: 5 ----\| Expected corrupted: 0
	aes_fi	51126580950499726674414093010482511474937231479619243034851782553793656915125	8126	----\| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL ----\| Expected: 3 ----\| Seen: 1 ----\| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1230) [aes_common_vseq] Check failed (vseq_done)				6 test runs
	aes_stress_all_with_rand_reset	10439205487283395448882473566795018751106254600109584189359828234224232136707	140	UVM_INFO @ 27171991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	95032062782505121381566456393431744470631017112061431707219120862124350028918	581	UVM_INFO @ 1001908097 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	86923539713669713909067008861063375512861007307894551059143696001744099959291	174	UVM_INFO @ 7326244 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	43955262726926547275195620389934272445300498015546561311363499529296418384580	188	UVM_INFO @ 53240835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	57159750242631737242516102025027815584974634545886702717270633688437556688774	205	UVM_INFO @ 24193022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	10585289392920885683822782985410097927603894276250170335503129214009810984825	160	UVM_INFO @ 7159749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues				5 test runs
	aes_stress_all	23783575777394319080369200253617902134105766605102017190339679195022222326942	28971	UVM_INFO @ 2391503139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	15412382156926845712868058102168743964613790188098252566998359427941378176122	268	UVM_INFO @ 135170849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	57784894099687570233463868822340588100657822073483803224993812949743454516339	202	UVM_INFO @ 92155692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_reseed	95612284694618369891668079310792314468694492769643164330175767188147701635211	5172	UVM_INFO @ 79335499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_stress_all_with_rand_reset	73927193476963265045684367136100525242296038864363251279179732051918898694162	587	UVM_INFO @ 1093191934 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_core_fi_vseq.sv:70) [aes_core_fi_vseq] wait timeout occurred!				4 test runs
	aes_core_fi	46347702582818243259911759698905708240663490781263224448924055014895450932859	151	UVM_INFO @ 10006371524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	1835263742243676416106799557209871667337794534068315288767952406855365314471	155	UVM_INFO @ 10005900489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	10650395212732790411203470785006678408120000645854601630393963085629569579376	154	UVM_INFO @ 10140871498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_core_fi	30564665208447850824060181696104359313610482810401432587443981336323867411617	147	UVM_INFO @ 10021006232 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				2 test runs
	aes_fi	78435752986721935137083012501933918023164047006030008074551497781267001356700	15998762	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	aes_alert_reset	42927262359475772460870080234408062363963543209497398960691658058698485576668	8157343	UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [aes_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				1 test run
	aes_tl_intg_err	70790210050430885675839685500154917610609314627521516766361637005729280695119	132	UVM_INFO @ 67381840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1391) [aes_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_fault does not trigger!				1 test run
	aes_shadow_reg_errors_with_csr_rw	72183451487093309461429197033922930520862456858561383937691266468064436618030	110	UVM_INFO @ 950141788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (aes_base_vseq.sv:87) [aes_stress_all_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)				1 test run
	aes_stress_all_with_rand_reset	34845859412298427055755666702163134173262795974540006797883382001124544352098	112	UVM_INFO @ 8645586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---