Simulation Results

Simulation Results: clkmgr

11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.66 %

code
70.05 %

assert
91.12 %

func
74.80 %

line
82.42 %

branch
87.53 %

cond
80.31 %

toggle
100.00 %

FSM
0.00 %

Validation stages

V1		78.26%
V2		70.94%
V2S		37.14%
V3		0.00%

18/23 passed

78.26 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	5.840s	363.935us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	1.170s	20.950us	1	1	100.00
csr_rw				4	5	80.00
	clkmgr_csr_rw	1.570s	46.409us	4	5	80.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	2.790s	75.714us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.970s	77.818us	1	1	100.00
csr_mem_rw_with_rand_reset				2	5	40.00
	clkmgr_csr_mem_rw_with_rand_reset	3.290s	113.327us	2	5	40.00
regwen_csr_and_corresponding_lockable_csr				5	6	83.33
	clkmgr_csr_rw	1.570s	46.409us	4	5	80.00
	clkmgr_csr_aliasing	1.970s	77.818us	1	1	100.00

83/117 passed

70.94 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	1.670s	52.926us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	3.430s	201.305us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	1.370s	39.286us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	5.840s	363.935us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.260s	25.237us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.000s	6.818us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.260s	25.237us	0	10	0.00
stress_all				1	10	10.00
	clkmgr_stress_all	12.700s	1340.821us	1	10	10.00
alert_test				10	10	100.00
	clkmgr_alert_test	2.820s	128.270us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	23.410s	1645.859us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	23.410s	1645.859us	25	25	100.00
tl_d_outstanding_access				7	12	58.33
	clkmgr_csr_hw_reset	1.170s	20.950us	1	1	100.00
	clkmgr_csr_rw	1.570s	46.409us	4	5	80.00
	clkmgr_csr_aliasing	1.970s	77.818us	1	1	100.00
	clkmgr_same_csr_outstanding	2.530s	118.106us	1	5	20.00
tl_d_partial_access				7	12	58.33
	clkmgr_csr_hw_reset	1.170s	20.950us	1	1	100.00
	clkmgr_csr_rw	1.570s	46.409us	4	5	80.00
	clkmgr_csr_aliasing	1.970s	77.818us	1	1	100.00
	clkmgr_same_csr_outstanding	2.530s	118.106us	1	5	20.00

V2S

39/105 passed

37.14 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				5	30	16.67
	clkmgr_sec_cm	12.940s	819.385us	5	5	100.00
	clkmgr_tl_intg_err	3.920s	225.700us	0	25	0.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	3.510s	188.547us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	3.510s	188.547us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	3.510s	188.547us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	3.510s	188.547us	20	20	100.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.330s	31.134us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	3.920s	225.700us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.260s	25.237us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.000s	6.818us	0	10	0.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	3.510s	188.547us	20	20	100.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	3.790s	217.721us	10	10	100.00
sec_cm_jitter_config_mubi				4	5	80.00
	clkmgr_csr_rw	1.570s	46.409us	4	5	80.00
sec_cm_idle_ctr_redun				5	5	100.00
	clkmgr_sec_cm	12.940s	819.385us	5	5	100.00
sec_cm_meas_config_regwen				4	5	80.00
	clkmgr_csr_rw	1.570s	46.409us	4	5	80.00
sec_cm_clk_ctrl_config_regwen				4	5	80.00
	clkmgr_csr_rw	1.570s	46.409us	4	5	80.00
prim_count_check				5	5	100.00
	clkmgr_sec_cm	12.940s	819.385us	5	5	100.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.080s	10.904us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	8.720s	423.758us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				25 test runs
	clkmgr_tl_intg_err	51259714011352932843663545045744290228994443622837210391531824510024341946483	103	UVM_INFO @ 10972019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	17927650152107573300444088365804499210137686360097267068160086076021728364253	84	UVM_INFO @ 35842485 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	5515502163340312406192230484445776112701501840066295146122996783476621768561	81	UVM_INFO @ 2613998 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	81536895153418933197696265257661735743861521863594601384069308263324708239355	81	UVM_INFO @ 1547164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	104463611406161070792933525910766928328322654355093951228428222369455485385062	106	UVM_INFO @ 68780784 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	109281328375298628758697144169804393379854576446767995733337133654230734761454	81	UVM_INFO @ 4912147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84998482703465185961596995519684249268659905691897674103480994351633804905383	81	UVM_INFO @ 3413699 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	66151642862187551602847351804799653996397782482288487637682382038650244461157	81	UVM_INFO @ 29366591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	64951583888105608074013416374574807470624470299488904691400676312866520260562	110	UVM_INFO @ 65698197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	44565236600978022639968005097294236750901330235724664445202747052494198158049	81	UVM_INFO @ 25230236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	76032503757077482198803715446185586285098571398958904679427010777467795308689	84	UVM_INFO @ 4398646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	50304953332006138754131395025067807416087083472744851016664844545638050965339	81	UVM_INFO @ 6546294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	96058775146227635793147423720357246623981262585306151678489215892805841768118	81	UVM_INFO @ 2853593 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	3895669201762550048294196528496982847737449975577129156459908415809043752431	84	UVM_INFO @ 8162521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	102658423959936997892652123119005998990912232378606824477383884580552860329799	84	UVM_INFO @ 7221481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	104848388291227558274953923600031082493734305330774754266450663745871677067755	81	UVM_INFO @ 5066227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	5969055439019923790532408594480772243568491553952417068455280228122876242711	81	UVM_INFO @ 7569446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	36670118665287765529502693488184776967944349775610851909061393483397983946574	99	UVM_INFO @ 15219283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	52500373244425566676755968637659920307485640764512846613553960939844935918888	81	UVM_INFO @ 6497403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	56714318258464699971650779493220683665955450482879314955687516782406976835743	91	UVM_INFO @ 4944974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	72610408695020595206381285858886438692887455674836994844700184935265249371649	88	UVM_INFO @ 3871179 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	14370953525240672949378578345562919775380082969983510214772190566909490752261	88	UVM_INFO @ 2626437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	21555754601044879612597439167441499124845843826628454062861112418922727599276	92	UVM_INFO @ 17335454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	113048671246678204096923409966790604922841094543241431459745928806244147373164	146	UVM_INFO @ 104965374 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	43573115221144146394424845705318586910191617932953802328817860908595135024939	88	UVM_INFO @ 2117843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				24 test runs
	clkmgr_frequency_timeout	59636634552341715001291022619387816142857615484624808938446355308177271123339	84	UVM_INFO @ 4087456 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	41514625795570611285549882262290737931460898235468935741957869685750234710885	85	UVM_INFO @ 3657060 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	78681619037482755846646023739907898319395361353131253361669236244773602944227	84	UVM_INFO @ 4277698 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	112732432025637149379669547101516835155759115254899673913200217874458591960122	84	UVM_INFO @ 2882526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	103662824985485948333617601132150156864064646222682362472556066940769287935303	85	UVM_INFO @ 8924360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	13996926209558289264018970589247233791518284432612275203157243246752742715410	83	UVM_INFO @ 2518642 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	95374864207436750269757832374477738163757797933179338868367603264662246811666	85	UVM_INFO @ 12784173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	112733520275725885754005031958464670886358060499792914571066966708302219775886	83	UVM_INFO @ 3045560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	112124349902212313885781981492327767515577707226787031246857572057549681031436	237	UVM_INFO @ 423757736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	29376279327070826695907192983567431984620889833254112115098803366541342962145	83	UVM_INFO @ 22859267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	84690025651566708283777231146316207708216697882830178815280397542655822258258	83	UVM_INFO @ 3157383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	8856970813975704849234653736931376951361528542345052579700476051576549184076	83	UVM_INFO @ 38876163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	110330634222098586547722811074810532360558037677674443193269446218281129266230	84	UVM_INFO @ 2287575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	54196698855586481446797878862313510299849613810757088126828897375919815277551	85	UVM_INFO @ 1960635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	87092889976480182285856117507394826367021317920013824192694306897319496318655	83	UVM_INFO @ 4532171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	51772163404313871756305697092137675596157543807343429637397567794795433157409	85	UVM_INFO @ 11825464 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	77408098057648451717978700066369534546643195651853369582615045149986484951474	84	UVM_INFO @ 5640197 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	54872951523683289895664926743802144581129956607292885497901381767441349851042	97	UVM_INFO @ 81142047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	56920676295270576943342114803284302271933494320012011674890480927495835968371	84	UVM_INFO @ 48616664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	83979898221220915872249482097137661075941818789700223152727605969812159735254	84	UVM_INFO @ 7110070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	77263607148695110297659051662695107764281140150133660175898249808769897215163	125	UVM_INFO @ 216288707 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	115482472794816870819999704173626824317479049108623992880037689872138459724548	83	UVM_INFO @ 5212184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	32210661023538876894123296281040690964584609152046104908870389950575523371366	84	UVM_INFO @ 6817588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	70272893009385488309851526717336357032732397619729643064622896362612375073736	84	UVM_INFO @ 6728842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				24 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	111460262833393006885947580601852080132401011164433838208644686767625817276754	81	UVM_INFO @ 3618131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	19232138132089877285193661112336186648839958764741666290958064694117218195422	88	UVM_INFO @ 28140491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	55641580029594032192212011020317564704967231143197991013237991636464838215625	81	UVM_INFO @ 34529645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	58238583055582672931440056767949711810388365375115586140356453308292095017685	82	UVM_INFO @ 43221383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	70371270594528425770028874513156804020970894476739917720603984123223287053062	81	UVM_INFO @ 2710136 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	3933868464592203897291594253902402626127168999766884495227664221867840451919	82	UVM_INFO @ 28198416 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	75637336235000280557087054263173532683658983451733412176810292504258173596827	118	UVM_INFO @ 225700234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	82745173695323870692998940819794871192684978482817388001902807144400762814019	81	UVM_INFO @ 3388015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	60330750114915226516999940721189661136961721599520261553264447749946379347281	81	UVM_INFO @ 31134367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	113903565340454679900220992118990676148443867566730514604578342400142606470509	91	UVM_INFO @ 10204885 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	111596438114844303923461513963816102887527884335786119470669256367308635173004	81	UVM_INFO @ 8223832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	51974021336957198816012178337330205127708324972825463056287212959256086947201	81	UVM_INFO @ 2081887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	93716723828827538423049465839623412747475315242444597112765304142930766041388	81	UVM_INFO @ 4190325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	80469862184271180627963607495106699819410761769825552735711017095506545711067	81	UVM_INFO @ 2526431 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	15592519401202972253257826504083262422261753293567312684405811807735057088309	81	UVM_INFO @ 6142261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	4627871667937109544693229047586266772251311243183668624792993576250097156779	84	UVM_INFO @ 3421302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	42611149550472581846620344770321686362735993630591114567252455264663618694687	81	UVM_INFO @ 17004977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	75755965502714327245305068889714487566704791386548571312801404122613515525796	103	UVM_INFO @ 31197850 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	49615258299986971971019226151749463764835456595939682895310027088154037826442	84	UVM_INFO @ 2957202 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	107827508601767161656831602990950108753257326463706101280258866018194189677927	81	UVM_INFO @ 5391274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	102458031461553411556890492879002560958928581832661587810404148978459049653217	92	UVM_INFO @ 21096729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	16337014029758191810957643557770095413654870750381118177576720502695231186341	81	UVM_INFO @ 10025332 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	1123361584693931702934185389047079861247747675860886571729921193886381103689	81	UVM_INFO @ 2786124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	54755370662502498392798139808029983175624267093621292640221838225446041855978	84	UVM_INFO @ 4334343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				15 test runs
	clkmgr_frequency	38623827768712324517245947811364564468896913981194037964770966270778678871157	82	UVM_INFO @ 8470759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	74764607458573649103122185290254098140424354273176812445401655928638773552244	81	UVM_INFO @ 8672766 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	114624219881459928430470917181071046657253213425913635486358947164299337113749	174	UVM_INFO @ 67458292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	93844287505158562906023341658958216767466642613612747214368776057307666195043	81	UVM_INFO @ 15606710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	110049062460123434365449871852638321845001360639672339230245877255784389323371	82	UVM_INFO @ 12173974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	57184058568480267284118839829881804312661116203864546888290450861932235425759	81	UVM_INFO @ 6766367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	110723177233063003812172938029203582900640306652056237635101002270124276334999	81	UVM_INFO @ 7013451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	55373252445394269043451170588607320867195727258980812457938036615118617441295	84	UVM_INFO @ 270657206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	11911475082185094738871448204786186277257156989628905986089594410874217724923	82	UVM_INFO @ 6804499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	75467375117123749570753908147325506543632738317644574810033339792921850010242	81	UVM_INFO @ 13872847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	70553639114439609780155548213320970144347931610987288675042665795243725286708	81	UVM_INFO @ 184300723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	14096525179924146325541086817560647307675685682613725355231601557860692230774	82	UVM_INFO @ 25237010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	16001437538354451360205414287543401533267380968014767430263970243029469592776	82	UVM_INFO @ 12187237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	43395742855585868582148802241193854217430044680059351349358369219668460906425	84	UVM_INFO @ 5982021 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	80722657427724877240136426566576766465142164967282280844442458556166313680265	83	UVM_INFO @ 101403604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				5 test runs
	clkmgr_regwen	88446375389400337471779852712555754481012388624856579122214404199674059845786	80	UVM_INFO @ 4786802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	97380517901018379517912956537419721340653383148465043590437132061567821983993	80	UVM_INFO @ 8607387 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	49443606957066903840272891646321848627483861636610810782417228882039195128178	80	UVM_INFO @ 3460719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	18590291388846797754993786466246916452538080111595933604363083620671776128600	80	UVM_INFO @ 14398080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	7721127126522793457745185050173550254599158773973518133235678798962493371364	80	UVM_INFO @ 10904119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				5 test runs
	clkmgr_regwen	88707719083633845055037547565469616208885598164207558047541948987158142760322	80	UVM_INFO @ 7244018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	11822407481070870731441978717980928925623176126377027919289165167039499545600	80	UVM_INFO @ 11725157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	96368538124768121609411615213707469437920246991565137496482133021222451522316	80	UVM_INFO @ 8564205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	18094814595432693789466990330753047355365932938557079317828988587246687553025	80	UVM_INFO @ 4984649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	46243632594589959971889071044706596597343614270401264809266655641310806709409	80	UVM_INFO @ 6644835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				4 test runs
	clkmgr_same_csr_outstanding	11330034706263243546045646768598387577279836671367001254948226401661052178100	81	UVM_INFO @ 17847233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	33325420029052344504519868429074140363413611179871516241014170394723570484815	81	UVM_INFO @ 6242727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	75208294819606007172311212949592218752989092783158068587657869379585751791640	81	UVM_INFO @ 7277210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	44253353448070181834350244857139059360223170019738843251503177701395286673709	81	UVM_INFO @ 9692029 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	2794825458568185838140145416775582466906051197847373093241686774218242714978	81	UVM_INFO @ 75713909 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---