Simulation Results: csrng

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.07 %
  • code
  • 96.19 %
  • assert
  • 96.94 %
  • func
  • 92.09 %
  • block
  • 98.50 %
  • line
  • 99.54 %
  • branch
  • 96.32 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 4.000s 90.125us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 20.154us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 3.000s 25.215us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 29.000s 1134.066us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 124.448us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 4.000s 124.511us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 3.000s 25.215us 5 5 100.00
csrng_csr_aliasing 3.000s 124.448us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
alerts 500 500 100.00
csrng_alert 53.000s 3053.617us 500 500 100.00
err 500 500 100.00
csrng_err 8.000s 31.278us 500 500 100.00
cmds 25 25 100.00
csrng_cmds 240.000s 17664.708us 25 25 100.00
life cycle 25 25 100.00
csrng_cmds 240.000s 17664.708us 25 25 100.00
stress_all 25 25 100.00
csrng_stress_all 1704.000s 118974.649us 25 25 100.00
intr_test 10 10 100.00
csrng_intr_test 3.000s 52.447us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 4.000s 35.376us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 20.000s 931.646us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 20.000s 931.646us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 2.000s 20.154us 1 1 100.00
csrng_csr_rw 3.000s 25.215us 5 5 100.00
csrng_csr_aliasing 3.000s 124.448us 1 1 100.00
csrng_same_csr_outstanding 4.000s 87.876us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 2.000s 20.154us 1 1 100.00
csrng_csr_rw 3.000s 25.215us 5 5 100.00
csrng_csr_aliasing 3.000s 124.448us 1 1 100.00
csrng_same_csr_outstanding 4.000s 87.876us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
csrng_sec_cm 7.000s 124.915us 5 5 100.00
csrng_tl_intg_err 14.000s 1208.598us 25 25 100.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 4.000s 135.750us 25 25 100.00
csrng_csr_rw 3.000s 25.215us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 53.000s 3053.617us 500 500 100.00
sec_cm_intersig_mubi 25 25 100.00
csrng_stress_all 1704.000s 118974.649us 25 25 100.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
csrng_sec_cm 7.000s 124.915us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
csrng_sec_cm 7.000s 124.915us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
csrng_sec_cm 7.000s 124.915us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
csrng_sec_cm 7.000s 124.915us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
csrng_sec_cm 7.000s 124.915us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 53.000s 3053.617us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
sec_cm_constants_lc_gated 25 25 100.00
csrng_stress_all 1704.000s 118974.649us 25 25 100.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 53.000s 3053.617us 500 500 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
csrng_tl_intg_err 14.000s 1208.598us 25 25 100.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
csrng_sec_cm 7.000s 124.915us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
csrng_sec_cm 7.000s 124.915us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 23.000s 1416.318us 200 200 100.00
csrng_err 8.000s 31.278us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 375.000s 18973.226us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 8 test runs
csrng_stress_all_with_rand_reset 25473344555276811180192293235016196749050818145682477934629157341068334743724 127
UVM_INFO @ 63425926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 34655598075136310070708654222303023123016121976096863390872017964883478470207 154
UVM_INFO @ 4621743473 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 82412511252089281459034905694489519127929138391450462251026380668084817230794 120
UVM_INFO @ 44903853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 12829946992912454492530429022522811661330859180674632029230875505779383052112 176
UVM_INFO @ 2260525880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 80578436925260833013644350520801794995814487662253895946563027104107292318747 108
UVM_INFO @ 12598955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 36833002835972720692211202721734901202580709231074492459110005370165409401603 165
UVM_INFO @ 1305993589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 22639535933849425102218242286831896950166627111303137852639029719118193788895 142
UVM_INFO @ 784089031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 23742180573436779051922857440858790366619426240602731345893122368335357730966 111
UVM_INFO @ 39866186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:180) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all_with_rand_reset 53942073333483525604746704277538154235191874293606380544731857018195411859907 138
UVM_INFO @ 100420391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---