Simulation Results: dma

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.51 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 78.15 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 8.000s 1654.696us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 9.000s 1431.377us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 9.000s 920.208us 50 50 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 30.677us 1 1 100.00
csr_rw 5 5 100.00
dma_csr_rw 2.000s 14.290us 5 5 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 834.558us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 2.000s 157.357us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 171.415us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
dma_csr_rw 2.000s 14.290us 5 5 100.00
dma_csr_aliasing 2.000s 157.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 77.000s 24753.312us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 510.000s 25233.656us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 1337.000s 280761.837us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 1337.000s 280761.837us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 510.000s 25233.656us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 1286.000s 252984.466us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 1337.000s 280761.837us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 27.000s 1962.260us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 389.000s 45521.843us 3 3 100.00
alert_test 10 10 100.00
dma_alert_test 2.000s 11.631us 10 10 100.00
intr_test 10 10 100.00
dma_intr_test 2.000s 32.705us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
dma_tl_errors 5.000s 305.436us 25 25 100.00
tl_d_illegal_access 25 25 100.00
dma_tl_errors 5.000s 305.436us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
dma_csr_hw_reset 2.000s 30.677us 1 1 100.00
dma_csr_rw 2.000s 14.290us 5 5 100.00
dma_csr_aliasing 2.000s 157.357us 1 1 100.00
dma_same_csr_outstanding 4.000s 465.373us 5 5 100.00
tl_d_partial_access 12 12 100.00
dma_csr_hw_reset 2.000s 30.677us 1 1 100.00
dma_csr_rw 2.000s 14.290us 5 5 100.00
dma_csr_aliasing 2.000s 157.357us 1 1 100.00
dma_same_csr_outstanding 4.000s 465.373us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 36.000s 453.311us 5 5 100.00
dma_generic_stress 1286.000s 252984.466us 5 5 100.00
dma_handshake_stress 1337.000s 280761.837us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 12.000s 1479.191us 15 15 100.00
tl_intg_err 30 30 100.00
dma_tl_intg_err 5.000s 284.089us 25 25 100.00
dma_sec_cm 2.000s 10.896us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 279.000s 91509.022us 25 25 100.00
dma_longer_transfer 29.000s 1239.725us 5 5 100.00
dma_stress_all_with_rand_reset 18.000s 1309.914us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 6713657101001930692932857870709875322207487351631414863488561892541775744929 124
UVM_INFO @ 1309914417ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---