Simulation Results: edn/edn0

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.04 %
  • code
  • 95.28 %
  • assert
  • 98.23 %
  • func
  • 58.60 %
  • block
  • 96.99 %
  • line
  • 98.68 %
  • branch
  • 93.33 %
  • toggle
  • 89.13 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 57.576us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.000s 68.617us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 18.707us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 10.000s 324.443us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 2.000s 55.925us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 4.000s 384.768us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 18.707us 5 5 100.00
edn_csr_aliasing 2.000s 55.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 75.000s 2260.092us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 75.000s 2260.092us 100 100 100.00
genbits 100 100 100.00
edn_genbits 75.000s 2260.092us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 34.577us 20 20 100.00
alerts 200 200 100.00
edn_alert 4.000s 345.315us 200 200 100.00
errs 100 100 100.00
edn_err 4.000s 26.821us 100 100 100.00
disable 100 100 100.00
edn_disable 2.000s 38.333us 50 50 100.00
edn_disable_auto_req_mode 4.000s 23.608us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 10.000s 110.395us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 15.188us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 2.000s 79.884us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 7.000s 566.973us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 7.000s 566.973us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.000s 68.617us 1 1 100.00
edn_csr_rw 2.000s 18.707us 5 5 100.00
edn_csr_aliasing 2.000s 55.925us 1 1 100.00
edn_same_csr_outstanding 3.000s 83.313us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.000s 68.617us 1 1 100.00
edn_csr_rw 2.000s 18.707us 5 5 100.00
edn_csr_aliasing 2.000s 55.925us 1 1 100.00
edn_same_csr_outstanding 3.000s 83.313us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 13.000s 835.334us 5 5 100.00
edn_tl_intg_err 4.000s 170.329us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 19.588us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 4.000s 345.315us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 13.000s 835.334us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 13.000s 835.334us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 13.000s 835.334us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 13.000s 835.334us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 4.000s 345.315us 200 200 100.00
edn_sec_cm 13.000s 835.334us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 4.000s 345.315us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 170.329us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 30 100.00
edn_stress_all_with_rand_reset 179.000s 28172.012us 30 30 100.00