Simulation Results: edn/edn1

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 95.89 %
  • assert
  • 98.70 %
  • func
  • 92.23 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 94.77 %
  • toggle
  • 96.15 %
  • FSM
  • 95.45 %
Validation stages
V1
100.00%
V2
99.84%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.270s 20.283us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.090s 25.099us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.160s 14.710us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.030s 169.590us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.200s 13.150us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.490s 67.083us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.160s 14.710us 5 5 100.00
edn_csr_aliasing 1.200s 13.150us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.420s 362.154us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.420s 362.154us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.420s 362.154us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.440s 23.743us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.900s 283.240us 200 200 100.00
errs 100 100 100.00
edn_err 1.640s 30.099us 100 100 100.00
disable 99 100 99.00
edn_disable 1.240s 13.655us 50 50 100.00
edn_disable_auto_req_mode 1.720s 142.217us 49 50 98.00
stress_all 30 30 100.00
edn_stress_all 7.760s 431.437us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.170s 47.390us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.230s 51.616us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.660s 1686.708us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.660s 1686.708us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.090s 25.099us 1 1 100.00
edn_csr_rw 1.160s 14.710us 5 5 100.00
edn_csr_aliasing 1.200s 13.150us 1 1 100.00
edn_same_csr_outstanding 1.710s 35.052us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.090s 25.099us 1 1 100.00
edn_csr_rw 1.160s 14.710us 5 5 100.00
edn_csr_aliasing 1.200s 13.150us 1 1 100.00
edn_same_csr_outstanding 1.710s 35.052us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 5.610s 1354.869us 5 5 100.00
edn_tl_intg_err 3.530s 173.175us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.300s 19.034us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.900s 283.240us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.610s 1354.869us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 5.610s 1354.869us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 5.610s 1354.869us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 5.610s 1354.869us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.900s 283.240us 200 200 100.00
edn_sec_cm 5.610s 1354.869us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.900s 283.240us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 3.530s 173.175us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 30 100.00
edn_stress_all_with_rand_reset 172.410s 83891.112us 30 30 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
edn_disable_auto_req_mode 59571053130165766783809948699028174638475695812798169942529241447845601252880 96
UVM_INFO @ 500000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---