| V1 |
|
100.00% |
| V2 |
|
93.63% |
| V2S |
|
93.33% |
| V3 |
|
50.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 40 | 40 | 100.00 | |||
| gpio_smoke | 1.870s | 130.028us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown | 1.920s | 177.703us | 10 | 10 | 100.00 | |
| gpio_smoke_en_cdc_prim | 2.190s | 221.540us | 10 | 10 | 100.00 | |
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 2.430s | 395.881us | 10 | 10 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| gpio_csr_hw_reset | 1.120s | 109.509us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| gpio_csr_rw | 1.120s | 16.799us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| gpio_csr_bit_bash | 9.670s | 298.010us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| gpio_csr_aliasing | 1.390s | 38.518us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| gpio_csr_mem_rw_with_rand_reset | 1.390s | 22.692us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| gpio_csr_rw | 1.120s | 16.799us | 5 | 5 | 100.00 | |
| gpio_csr_aliasing | 1.390s | 38.518us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| direct_and_masked_out | 20 | 20 | 100.00 | |||
| gpio_random_dout_din | 1.940s | 359.849us | 10 | 10 | 100.00 | |
| gpio_random_dout_din_no_pullup_pulldown | 1.830s | 92.419us | 10 | 10 | 100.00 | |
| out_in_regs_read_write | 10 | 10 | 100.00 | |||
| gpio_dout_din_regs_random_rw | 1.360s | 57.150us | 10 | 10 | 100.00 | |
| gpio_interrupt_programming | 10 | 10 | 100.00 | |||
| gpio_intr_rand_pgm | 1.900s | 272.021us | 10 | 10 | 100.00 | |
| random_interrupt_trigger | 10 | 10 | 100.00 | |||
| gpio_rand_intr_trigger | 5.620s | 891.535us | 10 | 10 | 100.00 | |
| interrupt_and_noise_filter | 10 | 10 | 100.00 | |||
| gpio_intr_with_filter_rand_intr_event | 5.320s | 401.647us | 10 | 10 | 100.00 | |
| noise_filter_stress | 10 | 10 | 100.00 | |||
| gpio_filter_stress | 26.170s | 3212.638us | 10 | 10 | 100.00 | |
| regs_long_reads_and_writes | 10 | 10 | 100.00 | |||
| gpio_random_long_reg_writes_reg_reads | 6.420s | 179.879us | 10 | 10 | 100.00 | |
| full_random | 10 | 10 | 100.00 | |||
| gpio_full_random | 1.450s | 183.889us | 10 | 10 | 100.00 | |
| stress_all | 1 | 10 | 10.00 | |||
| gpio_stress_all | 139.840s | 40534.881us | 1 | 10 | 10.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| gpio_alert_test | 0.970s | 43.671us | 10 | 10 | 100.00 | |
| intr_test | 10 | 10 | 100.00 | |||
| gpio_intr_test | 0.980s | 42.278us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.690s | 264.734us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| gpio_tl_errors | 4.690s | 264.734us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 11 | 12 | 91.67 | |||
| gpio_csr_rw | 1.120s | 16.799us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.680s | 299.311us | 4 | 5 | 80.00 | |
| gpio_csr_aliasing | 1.390s | 38.518us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.120s | 109.509us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 11 | 12 | 91.67 | |||
| gpio_csr_rw | 1.120s | 16.799us | 5 | 5 | 100.00 | |
| gpio_same_csr_outstanding | 1.680s | 299.311us | 4 | 5 | 80.00 | |
| gpio_csr_aliasing | 1.390s | 38.518us | 1 | 1 | 100.00 | |
| gpio_csr_hw_reset | 1.120s | 109.509us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 28 | 30 | 93.33 | |||
| gpio_tl_intg_err | 3.510s | 1254.198us | 23 | 25 | 92.00 | |
| gpio_sec_cm | 1.230s | 98.151us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 23 | 25 | 92.00 | |||
| gpio_tl_intg_err | 3.510s | 1254.198us | 23 | 25 | 92.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| straps_data | 10 | 10 | 100.00 | |||
| gpio_rand_straps | 0.910s | 12.359us | 10 | 10 | 100.00 | |
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| gpio_stress_all_with_rand_reset | 10.690s | 501.390us | 0 | 10 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 50 | 50 | 100.00 | |||
| gpio_inp_prd_cnt | 0.950s | 29.139us | 50 | 50 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (gpio_scoreboard.sv:243) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) | 9 test runs | |||
| gpio_stress_all | 110107797947219290146139531319431194646242165754452793240615942636427870387918 | 86 |
UVM_INFO @ 786308793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 28865520634794886523098668126265554027306127570837751649719795155978244213056 | 1601 |
UVM_INFO @ 13055556482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 77947813534663417319528432855973490848080860238647903783088789422831389125546 | 2822 |
UVM_INFO @ 40534881195 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 114571890941253978236667257782822457812210666123259326155404282224349593170059 | 143 |
UVM_INFO @ 2588540365 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 103451352252413214034269140641626268789027832317634673153959716540014961910404 | 569 |
UVM_INFO @ 590265838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 103124633464837352502786826991416529685832588497121824848458764572942035798322 | 1360 |
UVM_INFO @ 8145227860 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 102236697918496612642606689249076456063951328731091050410962339442641418462383 | 81 |
UVM_INFO @ 159836705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 71569482266592905551280094600571605817158859103604645632563303527274641209158 | 2378 |
UVM_INFO @ 3734739369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all | 26967782831473715963026843432567354872939280280479965331829991220741146423375 | 1542 |
UVM_INFO @ 13801920781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL (cip_base_vseq.sv:1230) [gpio_common_vseq] Check failed (vseq_done) | 7 test runs | |||
| gpio_stress_all_with_rand_reset | 94969484809448865811881996049886266652134327282807988985086688915596933818035 | 86 |
UVM_INFO @ 23238637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 14147789095290323146869329312716219754913673910333293508747634958533761406626 | 86 |
UVM_INFO @ 22838123 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 16468067782793446055264222526900911113686608964204832635987699307416074426952 | 141 |
UVM_INFO @ 501389726 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 108036067957223697501578055644478309658463953706932540021448625219344067764628 | 86 |
UVM_INFO @ 18800557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 40451861943375148230350290547914176503820550689997224221414579892063536502685 | 90 |
UVM_INFO @ 3683619615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 48419427815810148826692956095996885756804061781185638046721952238640318396266 | 230 |
UVM_INFO @ 237974156 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 27923803221933509564725788602806967308805611402882116323804603806115987198822 | 107 |
UVM_INFO @ 317232591 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* | 3 test runs | |||
| gpio_stress_all_with_rand_reset | 32512234293269360492690184245505888013948285548047692882000131933183830065122 | 88 |
UVM_INFO @ 5662349 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 48121959551826707835587032241488151122062933963989837961818027018851249929356 | 163 |
UVM_INFO @ 1248753340 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_stress_all_with_rand_reset | 72096667730078904464622695112862880571166448344513763454965709416045044989507 | 84 |
UVM_INFO @ 358280694 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: gpio_reg_block.inp_prd_cnt_ctrl_*.enable reset value: * | 2 test runs | |||
| gpio_tl_intg_err | 23788613626662916859460922724413745164731739089691354233349899249809309965469 | 149 |
UVM_INFO @ 101759541 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| gpio_tl_intg_err | 62026303808875318746645130196798677279888075105287856214807919067534530315804 | 345 |
UVM_INFO @ 179676918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (cip_base_vseq.sv:660) [gpio_common_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch | 1 test run | |||
| gpio_same_csr_outstanding | 68748478331342247966148991695795233216890129966789034234876290978179225542038 | 83 |
UVM_INFO @ 34049896 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|