Simulation Results: hmac

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.51 %
  • code
  • 83.35 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
98.57%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 18.000s 8667.756us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 139.211us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 2.000s 47.749us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 11.000s 3779.569us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.000s 363.398us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 1084.000s 239101.015us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 2.000s 47.749us 5 5 100.00
hmac_csr_aliasing 3.000s 363.398us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 113.000s 9415.958us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 123.000s 5872.485us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 369.000s 10750.083us 30 30 100.00
hmac_test_sha384_vectors 753.000s 20095.071us 75 75 100.00
hmac_test_sha512_vectors 734.000s 39316.128us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 1926.300us 50 50 100.00
hmac_test_hmac384_vectors 22.000s 2301.075us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 622.905us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 71.000s 20320.809us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 388.000s 23765.919us 10 10 100.00
error 10 10 100.00
hmac_error 114.000s 9002.389us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 127.000s 9395.329us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 18.000s 8667.756us 10 10 100.00
hmac_long_msg 113.000s 9415.958us 10 10 100.00
hmac_back_pressure 123.000s 5872.485us 25 25 100.00
hmac_datapath_stress 388.000s 23765.919us 10 10 100.00
hmac_burst_wr 71.000s 20320.809us 50 50 100.00
hmac_stress_all 1062.000s 209879.944us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 18.000s 8667.756us 10 10 100.00
hmac_long_msg 113.000s 9415.958us 10 10 100.00
hmac_back_pressure 123.000s 5872.485us 25 25 100.00
hmac_datapath_stress 388.000s 23765.919us 10 10 100.00
hmac_wipe_secret 127.000s 9395.329us 10 10 100.00
hmac_test_sha256_vectors 369.000s 10750.083us 30 30 100.00
hmac_test_sha384_vectors 753.000s 20095.071us 75 75 100.00
hmac_test_sha512_vectors 734.000s 39316.128us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 1926.300us 50 50 100.00
hmac_test_hmac384_vectors 22.000s 2301.075us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 622.905us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 18.000s 8667.756us 10 10 100.00
hmac_long_msg 113.000s 9415.958us 10 10 100.00
hmac_back_pressure 123.000s 5872.485us 25 25 100.00
hmac_datapath_stress 388.000s 23765.919us 10 10 100.00
hmac_burst_wr 71.000s 20320.809us 50 50 100.00
hmac_error 114.000s 9002.389us 10 10 100.00
hmac_wipe_secret 127.000s 9395.329us 10 10 100.00
hmac_test_sha256_vectors 369.000s 10750.083us 30 30 100.00
hmac_test_sha384_vectors 753.000s 20095.071us 75 75 100.00
hmac_test_sha512_vectors 734.000s 39316.128us 75 75 100.00
hmac_test_hmac256_vectors 20.000s 1926.300us 50 50 100.00
hmac_test_hmac384_vectors 22.000s 2301.075us 60 60 100.00
hmac_test_hmac512_vectors 28.000s 622.905us 75 75 100.00
hmac_stress_all 1062.000s 209879.944us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1062.000s 209879.944us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 14.298us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 16.972us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 5.000s 243.038us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 5.000s 243.038us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 139.211us 1 1 100.00
hmac_csr_rw 2.000s 47.749us 5 5 100.00
hmac_csr_aliasing 3.000s 363.398us 1 1 100.00
hmac_same_csr_outstanding 3.000s 524.859us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 139.211us 1 1 100.00
hmac_csr_rw 2.000s 47.749us 5 5 100.00
hmac_csr_aliasing 3.000s 363.398us 1 1 100.00
hmac_same_csr_outstanding 3.000s 524.859us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 1366.320us 5 5 100.00
hmac_tl_intg_err 5.000s 141.255us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 5.000s 141.255us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 18.000s 8667.756us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.000s 131.711us 25 25 100.00
stress_all_with_rand_reset 34 35 97.14
hmac_stress_all_with_rand_reset 262.000s 5842.710us 34 35 97.14
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 5.000s 535.069us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [hmac_common_vseq] wait timeout occurred! 1 test run
hmac_stress_all_with_rand_reset 61346078188081345954018762204471653457436960212001079749780994340561724867473 19662
UVM_INFO @ 28353184654 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---