Simulation Results: keymgr_dpe/darjeeling

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 65.88 %
  • code
  • 82.56 %
  • assert
  • 97.20 %
  • func
  • 17.88 %
  • block
  • 98.04 %
  • line
  • 98.70 %
  • branch
  • 93.63 %
  • toggle
  • 56.39 %
  • FSM
  • 81.54 %
Validation stages
V1
95.65%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 9 10 90.00
keymgr_dpe_smoke 21.000s 9905.421us 9 10 90.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 2.000s 27.754us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 2.000s 85.133us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 7.000s 1025.956us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 2.000s 29.973us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 2.000s 178.241us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 2.000s 85.133us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 29.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 17.835us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 2.000s 70.554us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 170.779us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 4.000s 170.779us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 27.754us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 85.133us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 29.973us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 80.829us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 2.000s 27.754us 1 1 100.00
keymgr_dpe_csr_rw 2.000s 85.133us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 29.973us 1 1 100.00
keymgr_dpe_same_csr_outstanding 3.000s 80.829us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 11.000s 1100.084us 5 5 100.00
keymgr_dpe_tl_intg_err 7.000s 843.595us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 317.460us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 317.460us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 317.460us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 3.000s 317.460us 20 20 100.00
shadow_reg_update_error_with_csr_rw 19 20 95.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 7.000s 284.481us 19 20 95.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 11.000s 1100.084us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 11.000s 1100.084us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error 1 test run
keymgr_dpe_smoke 43963965240440519341113830958234075304809656158881305339405004540550498853054 1943
UVM_INFO @ 216784703 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1391) [keymgr_dpe_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault_err does not trigger! 1 test run
keymgr_dpe_shadow_reg_errors_with_csr_rw 110490930593233164789403728384801528539349704873271855326584987547574986092082 85
UVM_INFO @ 167239632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---