Simulation Results: otbn

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.49 %
  • code
  • 86.71 %
  • assert
  • 90.77 %
  • func
  • 100.00 %
  • block
  • 99.32 %
  • line
  • 99.52 %
  • branch
  • 95.03 %
  • toggle
  • 86.08 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
93.53%
V2S
96.66%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 51.954us 1 1 100.00
otbn_smoke_vectorized 9.000s 21.306us 1 1 100.00
single_binary 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 5.000s 22.947us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 5.000s 17.003us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 7.000s 171.202us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 8.000s 54.307us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 58.065us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 5.000s 17.003us 5 5 100.00
otbn_csr_aliasing 8.000s 54.307us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 62.000s 1865.340us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 14.000s 308.017us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 47.000s 129.724us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 55.000s 673.127us 1 1 100.00
wfi 2 7 28.57
otbn_wfi_smoke 6.000s 20.572us 0 1 0.00
otbn_wfi_sec_wipe 8.000s 28.163us 2 5 40.00
otbn_wfi_back_to_back 6.000s 8.578us 0 1 0.00
back_to_back 8 10 80.00
otbn_multi 566.000s 1975.192us 8 10 80.00
stress_all 9 10 90.00
otbn_stress_all 184.000s 379.541us 9 10 90.00
lc_escalation 58 60 96.67
otbn_escalate 24.000s 313.891us 58 60 96.67
zero_state_err_urnd 4 5 80.00
otbn_zero_state_err_urnd 10.000s 62.790us 4 5 80.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 51.000s 135.998us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 12.000s 44.039us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 6.000s 19.202us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 9.000s 148.821us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 9.000s 148.821us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 5.000s 22.947us 1 1 100.00
otbn_csr_rw 5.000s 17.003us 5 5 100.00
otbn_csr_aliasing 8.000s 54.307us 1 1 100.00
otbn_same_csr_outstanding 5.000s 30.805us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 5.000s 22.947us 1 1 100.00
otbn_csr_rw 5.000s 17.003us 5 5 100.00
otbn_csr_aliasing 8.000s 54.307us 1 1 100.00
otbn_same_csr_outstanding 5.000s 30.805us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 14.000s 111.740us 10 10 100.00
otbn_dmem_err 15.000s 34.867us 15 15 100.00
internal_integrity 14 17 82.35
otbn_alu_bignum_mod_err 15.000s 927.299us 4 5 80.00
otbn_controller_ispr_rdata_err 39.000s 134.551us 5 5 100.00
otbn_mac_bignum_acc_err 17.000s 75.377us 5 5 100.00
otbn_urnd_err 13.000s 26.816us 0 2 0.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 10.000s 40.668us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 9.000s 26.761us 2 2 100.00
otbn_non_sec_partial_wipe 10 10 100.00
otbn_partial_wipe 9.000s 38.931us 10 10 100.00
tl_intg_err 30 30 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
otbn_tl_intg_err 40.000s 209.519us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 56.000s 798.367us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 51.954us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 15.000s 34.867us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 14.000s 111.740us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 40.000s 209.519us 25 25 100.00
sec_cm_controller_fsm_global_esc 58 60 96.67
otbn_escalate 24.000s 313.891us 58 60 96.67
sec_cm_controller_fsm_local_esc 39 40 97.50
otbn_imem_err 14.000s 111.740us 10 10 100.00
otbn_dmem_err 15.000s 34.867us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 62.790us 4 5 80.00
otbn_illegal_mem_acc 10.000s 40.668us 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 14.000s 111.740us 10 10 100.00
otbn_dmem_err 15.000s 34.867us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 62.790us 4 5 80.00
otbn_illegal_mem_acc 10.000s 40.668us 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 58 60 96.67
otbn_escalate 24.000s 313.891us 58 60 96.67
sec_cm_start_stop_ctrl_fsm_local_esc 39 40 97.50
otbn_imem_err 14.000s 111.740us 10 10 100.00
otbn_dmem_err 15.000s 34.867us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 62.790us 4 5 80.00
otbn_illegal_mem_acc 10.000s 40.668us 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 10.000s 50.014us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 11.000s 26.937us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 118.000s 372.558us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 118.000s 372.558us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 13.000s 41.266us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 9 10 90.00
otbn_rf_bignum_intg_err 66.000s 318.249us 9 10 90.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 84.000s 290.468us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 84.000s 290.468us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 24.000s 49.247us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
sec_cm_write_mem_integrity 8 10 80.00
otbn_multi 566.000s 1975.192us 8 10 80.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 15.000s 34.923us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 48.000s 540.797us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 778.000s 3443.157us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
otbn_stress_all_with_rand_reset 24.000s 56.805us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 10 test runs
otbn_stress_all_with_rand_reset 65600834844434307481366028946263873362648417680718880120389552913215430568028 148
UVM_INFO @ 40732779 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 95336024767125783530141042649201669996351722041785645864102050600778074489492 151
UVM_INFO @ 33291931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 113702620030236841733365806641033710043247689458603181067049913187874321049770 156
UVM_INFO @ 25235212 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 107274532808121607645325206470350475573300612257241438383950393113890284926062 152
UVM_INFO @ 25175064 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 14724325501971399567237935247442123980521346871935992449528649578095101177792 146
UVM_INFO @ 40337135 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 41165638497209279610043027745223680172560492092964319478886084075916367355573 149
UVM_INFO @ 21697925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 69257544746135082225993659692873681618015859049980521492399896405268695562424 148
UVM_INFO @ 11732537 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 35491212742631606131611614414317424111428266801856212629226246844858013414363 165
UVM_INFO @ 56804894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 106745390325919732161202936066417163211611611853326229344474269231121360153381 152
UVM_INFO @ 62806739 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 8310852738298137982596009344666337305216999416806158135690034227240545945368 160
UVM_INFO @ 54384682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value. 3 test runs
otbn_wfi_sec_wipe 22902774280684523170435755881451692857635508778436948246040844556898276410737 113
UVM_FATAL @ 5123870 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 5123870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_sec_wipe 10511640913595238175432195966682732681054295848789353883981727075408601704423 113
UVM_FATAL @ 21478419 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 21478419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_sec_wipe 43741500823240194953784468349594197369856571325722523511951772084191766388216 110
UVM_FATAL @ 4857412 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 4857412 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 2 test runs
otbn_urnd_err 7037696964874886757129928356687328368112308549902678813044256928097639554513 113
UVM_ERROR @ 14222133 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 14222133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_urnd_err 25398066194166646546282307426880938240759349508886874183263346109454982552131 115
UVM_ERROR @ 26815744 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 26815744 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. 2 test runs
otbn_wfi_smoke 24409269897763955152920729589106640447725996822165874781442816165592910712386 115
UVM_INFO @ 20571731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_back_to_back 79010358280432692310194630336916188822377918747997774282782537826765340581610 113
UVM_INFO @ 8577918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,158): Assertion NoModelErrs has failed 2 test runs
otbn_zero_state_err_urnd 36962029392305812005170492338221993339631319896745022135399284577912383373134 115
UVM_ERROR @ 14787218 ps: (otbn_model_if.sv:158) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 14787218 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 45133523303726989502661531102980018890232782144255195324553200996235521485525 126
UVM_ERROR @ 50233772 ps: (otbn_model_if.sv:158) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 50233772 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 2 test runs
otbn_stack_addr_integ_chk 99220601099913560233807208620852814019271285302899779761587039200867641053747 114
UVM_ERROR @ 4759976 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 4759976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 114630342111888312109510254665450590615175478225956151460497318282712125640269 115
UVM_ERROR @ 164507620 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 164507620 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 44603823479684480296855231377654443430151460048423522357735592208576252097297 91
UVM_INFO @ 24248851 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
otbn_alu_bignum_mod_err 104735127565893671353534458796961362523891259721624928549874326199630269106069 113
UVM_INFO @ 88572614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_base_vseq.sv:428) [otbn_single_vseq] Check failed exp_end_addr == cfg.model_agent_cfg.vif.stop_pc (* [*] vs * [*]) 1 test run
otbn_stress_all 23394551347357217636901130033089291670542712413937133787923719077988007045700 176
UVM_INFO @ 1152986462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_multi 22754929891315850544601517772126753746472474119798136148265102466404565042602 166
UVM_INFO @ 222199645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_multi 4122970639263159894170831325848748091224895562106186403381011306117352651497 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 91719925209340395450083486959514954361871246237451372440103588289496678533876 108
UVM_INFO @ 3257443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---