Simulation Results: rom_ctrl/32kb

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.21 %
  • code
  • 79.91 %
  • assert
  • 97.67 %
  • func
  • 99.05 %
  • block
  • 78.65 %
  • line
  • 79.01 %
  • branch
  • 79.77 %
  • toggle
  • 84.69 %
  • FSM
  • 76.19 %
Validation stages
V1
100.00%
V2
78.87%
V2S
66.10%
V3
15.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.000s 1796.072us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 75.994us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 2.000s 190.051us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 77.324us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 72.335us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 516.341us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 2.000s 190.051us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 72.335us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 74.066us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 64.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 4.000s 171.450us 0 2 0.00
stress_all 7 20 35.00
rom_ctrl_stress_all 10801.000s 0.000us 7 20 35.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 5.000s 386.377us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 7.000s 53.850us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 8.000s 79.477us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 8.000s 79.477us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 75.994us 1 1 100.00
rom_ctrl_csr_rw 2.000s 190.051us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 72.335us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 143.369us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 75.994us 1 1 100.00
rom_ctrl_csr_rw 2.000s 190.051us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 72.335us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 143.369us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 727.043us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 149.000s 1040.773us 5 5 100.00
rom_ctrl_tl_intg_err 36.000s 295.781us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 149.000s 1040.773us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 149.000s 1040.773us 5 5 100.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 149.000s 1040.773us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 149.000s 1040.773us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.000s 1796.072us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.000s 1796.072us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.000s 1796.072us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 36.000s 295.781us 25 25 100.00
sec_cm_bus_local_esc 2 22 9.09
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
rom_ctrl_kmac_err_chk 5.000s 386.377us 2 2 100.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 8.000s 727.043us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 149.000s 1040.773us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 3 20 15.00
rom_ctrl_stress_all_with_rand_reset 3600.000s 0.000us 3 20 15.00

Error Messages

   Test seed line log context
Job timed out after * minutes 38 test runs
rom_ctrl_corrupt_sig_fatal_chk 35414738626901769588461199502005493041436644238812688809428208689064437452101 None
rom_ctrl_stress_all 16960964879347573010305402885821316236831197478627212951150464400557384948460 None
rom_ctrl_corrupt_sig_fatal_chk 25039665509407048988218828120470979131658917715722395272057480591017546328704 None
rom_ctrl_stress_all 86699587507041701970227214290732730265499437912689548711499876295160186950842 None
rom_ctrl_corrupt_sig_fatal_chk 98362933902057985678671075884594905351065133513717337588323217337683515008181 None
rom_ctrl_stress_all 31034552678075585880800701881390827522797034477585386996742884252912597990823 None
rom_ctrl_corrupt_sig_fatal_chk 7986016970035945272472696466204132436910512614726863901002832236980219049576 None
rom_ctrl_stress_all 30855972960248261926071303532906890836966718802936836716320420085077910493454 None
rom_ctrl_corrupt_sig_fatal_chk 32332577252191841058496289991106417713222776635884192063603759280674850115247 None
rom_ctrl_stress_all_with_rand_reset 72257980907269111337509752287140194666376061094323101615773919719900061112986 None
rom_ctrl_corrupt_sig_fatal_chk 100426220130077553321265753159437804147936882306730633801059442670957711946414 None
rom_ctrl_stress_all 115383170430251665875231977739623085759314591325128542189544297544402017708121 None
rom_ctrl_corrupt_sig_fatal_chk 42072727960271587012040037599538959996859293176164046988470097860196559958232 None
rom_ctrl_stress_all_with_rand_reset 56120799366895946934034471966814249145556527104890078929876937526016290298923 None
rom_ctrl_stress_all 58316071272661750356193943447176466405773101914420816963742665659321113504965 None
rom_ctrl_corrupt_sig_fatal_chk 53495570212542592093879584823434446569212454451376569607477434140672537159540 None
rom_ctrl_stress_all_with_rand_reset 66791621592585742561903544557223016654844757180577706420678341533160406329457 None
rom_ctrl_corrupt_sig_fatal_chk 73296480326756760720019554675421768259841105399354772676497217780212473133632 None
rom_ctrl_stress_all 89223672489382768073264022182957525646444039177299533424159749192463629675493 None
rom_ctrl_corrupt_sig_fatal_chk 60156676537047024879302736062509755734166448382084111437687135775078338529215 None
rom_ctrl_stress_all 31553362477069521888823203187362409235505016217764248970918747505651310437935 None
rom_ctrl_corrupt_sig_fatal_chk 71729880481749537949288129160845285401682117397853217668093345346095864543471 None
rom_ctrl_stress_all 73759931403761094888498735365963077839792496639480737268921362039286750245426 None
rom_ctrl_corrupt_sig_fatal_chk 109755842192880612963547588423294822532616129766994666864714923173409683975788 None
rom_ctrl_corrupt_sig_fatal_chk 95818374928239156949404154271514509805137822138199985873785191233816415003955 None
rom_ctrl_stress_all_with_rand_reset 28025707699919651233300163853781830189613657573705245123886713915062158642068 None
rom_ctrl_corrupt_sig_fatal_chk 100377874729672525331009981951283833913857316858921824920697034616538716472740 None
rom_ctrl_stress_all_with_rand_reset 70511926250512722544630931479434883901957211649260049673190511563744627230542 None
rom_ctrl_corrupt_sig_fatal_chk 37009565441880779771539514469233464172320137795865263777770636387534588057896 None
rom_ctrl_stress_all 107752252363828077758028357900654981817395648027752178027068853960450115103637 None
rom_ctrl_corrupt_sig_fatal_chk 113494952680732386846675071166174222245867157467374073157212506420504179977852 None
rom_ctrl_corrupt_sig_fatal_chk 89760058343866620263290872309130221252216577050255251750693056886181296507152 None
rom_ctrl_stress_all 80850001945398849493260514548702726692298306150534952191565939953153821553919 None
rom_ctrl_corrupt_sig_fatal_chk 70793558914346418341338082335251403303390205848159122244590505598580568761101 None
rom_ctrl_stress_all_with_rand_reset 44642940318836611439259733478904219452288924359946980740071629555567886312830 None
rom_ctrl_stress_all 20185292265198675821214265514133238199545160887235941472454969968599807918754 None
rom_ctrl_corrupt_sig_fatal_chk 106851442450944647753967122012440560905450925531929653997510150263801302249245 None
rom_ctrl_corrupt_sig_fatal_chk 87193273382939303630528980245431494541264319935818300490166052110158856270525 None
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 11 test runs
rom_ctrl_stress_all_with_rand_reset 26705006740481747809365451739953456659394576334919746587173921731614329151036 105
UVM_INFO @ 2056852548 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 16502964174564361361951197705740449830639528159674725020429491106916570173057 91
UVM_INFO @ 459975883 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 54834740758699026264706529171578865280715347513795717271564161949966095066020 90
UVM_INFO @ 438243977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all 27184770860256958487002293239637064930489043762240288639726610812126045328403 87
UVM_INFO @ 175199756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 7010859038357863565984105740629441447043506849479182823866594392554635368024 139
UVM_INFO @ 2223882653 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 12835501942607159039697695986157925713285056426955349611267936688996917793275 100
UVM_INFO @ 618687301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 70009699959817443239669013057872267487473083328917078443133629710159895466761 124
UVM_INFO @ 2524002427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 71782059470690013132444105872488417265863038173600241250145472944615499921134 102
UVM_INFO @ 1145684343 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 113287869639240875254735176713973872090369196600197551912988887393649627213255 92
UVM_INFO @ 2205383497 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 88496498374608343821091066567507435260504627084871687556553355077722221622478 90
UVM_INFO @ 734431742 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 1464808836255407487825246453595005589583090449380915231456439261099767797285 120
UVM_INFO @ 885636758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 62673480973321235878474051438120516976107271441041093692934076275174553480647 88
UVM_INFO @ 163460169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 89431883196431924803991596922259084941097626984233698632355286983318549086517 88
UVM_INFO @ 171449954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rom_ctrl_common_vseq] Check failed (vseq_done) 1 test run
rom_ctrl_stress_all_with_rand_reset 110302444876357011982879542277815069893624508810055240208533046835129798245913 91
UVM_INFO @ 8021746 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---