Simulation Results: rom_ctrl/64kb

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.90 %
  • code
  • 85.19 %
  • assert
  • 97.23 %
  • func
  • 99.29 %
  • block
  • 79.23 %
  • line
  • 79.37 %
  • branch
  • 81.40 %
  • toggle
  • 84.74 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
77.46%
V2S
62.71%
V3
40.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.000s 1486.451us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.000s 88.830us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 4.000s 53.584us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.000s 305.294us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.000s 56.331us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.000s 63.950us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 4.000s 53.584us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 56.331us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.000s 52.346us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.000s 56.655us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 3.000s 23.640us 0 2 0.00
stress_all 8 20 40.00
rom_ctrl_stress_all 10801.000s 0.000us 8 20 40.00
kmac_err_chk 0 2 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 2 0.00
alert_test 10 10 100.00
rom_ctrl_alert_test 4.000s 48.191us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 8.000s 373.015us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 8.000s 373.015us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.000s 88.830us 1 1 100.00
rom_ctrl_csr_rw 4.000s 53.584us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 56.331us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 69.055us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 6.000s 88.830us 1 1 100.00
rom_ctrl_csr_rw 4.000s 53.584us 5 5 100.00
rom_ctrl_csr_aliasing 3.000s 56.331us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.000s 69.055us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.000s 2050.865us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 276.000s 1749.252us 5 5 100.00
rom_ctrl_tl_intg_err 82.000s 1341.946us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 276.000s 1749.252us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 276.000s 1749.252us 5 5 100.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 276.000s 1749.252us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 276.000s 1749.252us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.000s 1486.451us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.000s 1486.451us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.000s 1486.451us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 82.000s 1341.946us 25 25 100.00
sec_cm_bus_local_esc 0 22 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
rom_ctrl_kmac_err_chk 3600.000s 0.000us 0 2 0.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 3601.000s 0.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.000s 2050.865us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 276.000s 1749.252us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 8 20 40.00
rom_ctrl_stress_all_with_rand_reset 3601.000s 0.000us 8 20 40.00

Error Messages

   Test seed line log context
Job timed out after * minutes 38 test runs
rom_ctrl_stress_all 55002581530734536964932324749205178591123748303699743988891620770336171387228 None
rom_ctrl_corrupt_sig_fatal_chk 94560832936449931326042477764726453976704046757446223520144366780086052437055 None
rom_ctrl_kmac_err_chk 68132486577792360092248994409868435233376654927398374455878662893116222413325 None
rom_ctrl_stress_all 60752533056998058514896077558227372799108918798871759129981953404726109216066 None
rom_ctrl_corrupt_sig_fatal_chk 51408074586949655448845555966496461942081739377334781149306848624563661563626 None
rom_ctrl_kmac_err_chk 104067242924871090513396608561411079757912723163135263697878432190195914182427 None
rom_ctrl_stress_all 34130714478047031070406562732805910794768004131541259409415501106429530118228 None
rom_ctrl_corrupt_sig_fatal_chk 29056278311975855353702723250476903657579643426546744628451784013314875804959 None
rom_ctrl_corrupt_sig_fatal_chk 45694866019222705795052839754226159971071503096522739647098837641420484295558 None
rom_ctrl_stress_all_with_rand_reset 40235960254444615001648681922245342769611341214596575303494589721237024792576 None
rom_ctrl_corrupt_sig_fatal_chk 114046055161450185776835470249515585246922057135210410200649440491237495568261 None
rom_ctrl_stress_all_with_rand_reset 91318441923411462928972083776425941932128619397593461628241537128607288391800 None
rom_ctrl_stress_all 56258933365498554860083723159016680593538958817508695627417738964745385473329 None
rom_ctrl_corrupt_sig_fatal_chk 99740737070793724794961491448297090526880308894112938805233371878079782975793 None
rom_ctrl_stress_all 17545113483715713355302465584457931713141506782500181148463446141391739831934 None
rom_ctrl_corrupt_sig_fatal_chk 30772163659435403274893628943448558552094891198673607768682377921030542389452 None
rom_ctrl_stress_all_with_rand_reset 56747347369106805574530694237854694968012380311377969859051916306634971962982 None
rom_ctrl_stress_all 75439471883711583688563246433490795465261485290012548396161368112075447217181 None
rom_ctrl_corrupt_sig_fatal_chk 31274311580960704884848324701219496954567216386084036734523629428971949444399 None
rom_ctrl_corrupt_sig_fatal_chk 66319132040582751966159618091285976254094604046620172219565553898951814869843 None
rom_ctrl_stress_all 9643556098480922164141340513412374312715025777123629676412223590082150734432 None
rom_ctrl_corrupt_sig_fatal_chk 70721184571037221409488634259609406238512037708350579910446710575376739047110 None
rom_ctrl_corrupt_sig_fatal_chk 35933468888781249569545670734073968082532374223063602132631184163742244785252 None
rom_ctrl_stress_all_with_rand_reset 68745897649322683917441325663238873958797643561815275010777060452702724232546 None
rom_ctrl_corrupt_sig_fatal_chk 2206307838102630875755074662295214492577521971620065310996373269683650505930 None
rom_ctrl_stress_all 69851199090979602208372792303892339058588242903523151226633044686200786989154 None
rom_ctrl_corrupt_sig_fatal_chk 43478140864092020956412689264259112122613832076211689982274246721239760551599 None
rom_ctrl_stress_all 80227299426491008045588235076943556830585929719871324856441559787467866908814 None
rom_ctrl_corrupt_sig_fatal_chk 113520547969944443893289322095718164321744125348456563868663496220099529307496 None
rom_ctrl_corrupt_sig_fatal_chk 74789271220123998879264333193728206650150943794670550202845657046304015586591 None
rom_ctrl_stress_all 19753556694343357947377708548930584008849822500754151885394208248567201680997 None
rom_ctrl_corrupt_sig_fatal_chk 99069368715846264265190504345745385407307736034586691257290876387723440365594 None
rom_ctrl_corrupt_sig_fatal_chk 62380331120976248857687898745348400696182038558711460558497432422869417752379 None
rom_ctrl_corrupt_sig_fatal_chk 54321682578474523514273844844036794953893911751754010269071738945065800525768 None
rom_ctrl_stress_all 103130108084610883430235683775514832390662476317206824513860876827478452977026 None
rom_ctrl_corrupt_sig_fatal_chk 7584272178598539429433895799419543634647826186763262797722284891683893034745 None
rom_ctrl_stress_all 56569574930484516148482933939987313148939806109515134177545942697907113965607 None
rom_ctrl_corrupt_sig_fatal_chk 64027803108218210026846928193601673501128144251747707448397598194203945382690 None
UVM_ERROR (cip_base_scoreboard.sv:425) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 8 test runs
rom_ctrl_stress_all_with_rand_reset 14821216604429841227534400590917552957382484495168301896649684606922367786714 98
UVM_INFO @ 3316837963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 93871001356230573709296994050307866196227051632517355638997800569852101954889 108
UVM_INFO @ 1641897904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 95283853030646797868544757038267698753378654076368516928942553078205283927157 102
UVM_INFO @ 3651315227 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 55334021180546306231778272470551398736588688373192933157151592848648212621786 106
UVM_INFO @ 2460648936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 100677971061381137232417047180331542211262007368060014113604082017139706105506 121
UVM_INFO @ 9081718114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 92141925576345664515510277031703035944037143082699727175761687497154364137888 106
UVM_INFO @ 1917151604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 60307293920788008876913631476621957515090381185311112153979100002081827569896 107
UVM_INFO @ 2239561024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 13532359579262636464157996989361445653586765376792521377220172605653043662451 131
UVM_INFO @ 2949579585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 35565125060525964595449246834794751968104827624842651545451705007608931155860 88
UVM_INFO @ 23639517 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 45553510391918767994990296585693353181725456127074664040928248127766626013663 88
UVM_INFO @ 2483774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---