Simulation Results

Simulation Results: rv_dm/use_dmi_interface

11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.80 %

code
83.27 %

assert
96.90 %

func
98.23 %

block
93.74 %

line
94.28 %

branch
83.03 %

toggle
75.39 %

FSM
80.36 %

Validation stages

V1		96.92%
V2		45.00%
V2S		96.00%
V3		10.00%
unmapped		0.00%

126/130 passed

96.92 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				2	2	100.00
	rv_dm_smoke	57.000s	1897.131us	2	2	100.00
jtag_dtm_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dtm_csr_hw_reset	52.000s	328.220us	5	5	100.00
jtag_dtm_csr_rw				20	20	100.00
	rv_dm_jtag_dtm_csr_rw	51.000s	183.038us	20	20	100.00
jtag_dtm_csr_bit_bash				5	5	100.00
	rv_dm_jtag_dtm_csr_bit_bash	82.000s	17172.178us	5	5	100.00
jtag_dtm_csr_aliasing				5	5	100.00
	rv_dm_jtag_dtm_csr_aliasing	51.000s	81.090us	5	5	100.00
jtag_dmi_csr_hw_reset				5	5	100.00
	rv_dm_jtag_dmi_csr_hw_reset	91.000s	17453.423us	5	5	100.00
jtag_dmi_csr_rw				20	20	100.00
	rv_dm_jtag_dmi_csr_rw	73.000s	12293.314us	20	20	100.00
jtag_dmi_csr_bit_bash				20	20	100.00
	rv_dm_jtag_dmi_csr_bit_bash	181.000s	59616.593us	20	20	100.00
jtag_dmi_csr_aliasing				5	5	100.00
	rv_dm_jtag_dmi_csr_aliasing	59.000s	13940.619us	5	5	100.00
jtag_dmi_cmderr_busy				2	2	100.00
	rv_dm_cmderr_busy	52.000s	198.303us	2	2	100.00
jtag_dmi_cmderr_not_supported				2	2	100.00
	rv_dm_cmderr_not_supported	51.000s	631.636us	2	2	100.00
cmderr_exception				2	2	100.00
	rv_dm_cmderr_exception	54.000s	599.832us	2	2	100.00
mem_tl_access_resuming				0	2	0.00
	rv_dm_mem_tl_access_resuming	50.000s	269.609us	0	2	0.00
mem_tl_access_halted				2	2	100.00
	rv_dm_mem_tl_access_halted	51.000s	224.573us	2	2	100.00
cmderr_halt_resume				2	2	100.00
	rv_dm_cmderr_halt_resume	54.000s	655.153us	2	2	100.00
dataaddr_rw_access				2	2	100.00
	rv_dm_dataaddr_rw_access	51.000s	415.285us	2	2	100.00
halt_resume				8	8	100.00
	rv_dm_halt_resume_whereto	54.000s	764.222us	8	8	100.00
progbuf_busy				2	2	100.00
	rv_dm_cmderr_busy	52.000s	198.303us	2	2	100.00
abstractcmd_status				2	2	100.00
	rv_dm_abstractcmd_status	52.000s	257.093us	2	2	100.00
progbuf_read_write_execute				2	2	100.00
	rv_dm_progbuf_read_write_execute	46.000s	1173.947us	2	2	100.00
progbuf_exception				2	2	100.00
	rv_dm_cmderr_exception	54.000s	599.832us	2	2	100.00
rom_read_access				0	2	0.00
	rv_dm_rom_read_access	50.000s	66.607us	0	2	0.00
csr_hw_reset				1	1	100.00
	rv_dm_csr_hw_reset	49.000s	286.058us	1	1	100.00
csr_rw				5	5	100.00
	rv_dm_csr_rw	52.000s	127.885us	5	5	100.00
csr_bit_bash				1	1	100.00
	rv_dm_csr_bit_bash	85.000s	2331.065us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_dm_csr_aliasing	45.000s	778.383us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	rv_dm_csr_mem_rw_with_rand_reset	54.000s	215.652us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	rv_dm_csr_aliasing	45.000s	778.383us	1	1	100.00
	rv_dm_csr_rw	52.000s	127.885us	5	5	100.00
mem_walk				1	1	100.00
	rv_dm_mem_walk	50.000s	55.718us	1	1	100.00
mem_partial_access				1	1	100.00
	rv_dm_mem_partial_access	40.000s	31.319us	1	1	100.00

81/180 passed

45.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
idcode				2	2	100.00
	rv_dm_smoke	57.000s	1897.131us	2	2	100.00
jtag_dtm_hard_reset				2	2	100.00
	rv_dm_jtag_dtm_hard_reset	52.000s	762.736us	2	2	100.00
jtag_dtm_idle_hint				2	2	100.00
	rv_dm_jtag_dtm_idle_hint	51.000s	244.000us	2	2	100.00
jtag_dmi_failed_op				2	2	100.00
	rv_dm_dmi_failed_op	56.000s	178.264us	2	2	100.00
jtag_dmi_dm_inactive				2	2	100.00
	rv_dm_jtag_dmi_dm_inactive	51.000s	404.639us	2	2	100.00
sba				0	40	0.00
	rv_dm_sba_tl_access	71.000s	10768.297us	0	20	0.00
	rv_dm_delayed_resp_sba_tl_access	53.000s	449.081us	0	20	0.00
bad_sba				2	20	10.00
	rv_dm_bad_sba_tl_access	59.000s	3169.094us	2	20	10.00
sba_autoincrement				6	20	30.00
	rv_dm_autoincr_sba_tl_access	109.000s	99719.117us	6	20	30.00
jtag_dmi_debug_disabled				0	2	0.00
	rv_dm_jtag_dmi_debug_disabled	53.000s	227.513us	0	2	0.00
sba_debug_disabled				2	2	100.00
	rv_dm_sba_debug_disabled	48.000s	1186.419us	2	2	100.00
ndmreset_req				2	2	100.00
	rv_dm_ndmreset_req	52.000s	912.186us	2	2	100.00
hart_unavail				0	5	0.00
	rv_dm_hart_unavail	52.000s	207.626us	0	5	0.00
tap_ctrl_transitions				11	11	100.00
	rv_dm_tap_fsm	71.000s	12314.111us	1	1	100.00
	rv_dm_tap_fsm_rand_reset	97.000s	3164.153us	10	10	100.00
hartsel_warl				1	1	100.00
	rv_dm_hartsel_warl	51.000s	385.396us	1	1	100.00
stress_all				0	20	0.00
	rv_dm_stress_all	10812.000s	0.000us	0	20	0.00
alert_test				10	10	100.00
	rv_dm_alert_test	51.000s	101.968us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	rv_dm_tl_errors	56.000s	1026.512us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	rv_dm_tl_errors	56.000s	1026.512us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	rv_dm_csr_aliasing	45.000s	778.383us	1	1	100.00
	rv_dm_csr_hw_reset	49.000s	286.058us	1	1	100.00
	rv_dm_csr_rw	52.000s	127.885us	5	5	100.00
	rv_dm_same_csr_outstanding	56.000s	2489.719us	5	5	100.00
tl_d_partial_access				12	12	100.00
	rv_dm_csr_aliasing	45.000s	778.383us	1	1	100.00
	rv_dm_csr_hw_reset	49.000s	286.058us	1	1	100.00
	rv_dm_csr_rw	52.000s	127.885us	5	5	100.00
	rv_dm_same_csr_outstanding	56.000s	2489.719us	5	5	100.00

V2S

48/50 passed

96.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				29	30	96.67
	rv_dm_sec_cm	53.000s	1320.779us	5	5	100.00
	rv_dm_tl_intg_err	70.000s	6567.488us	24	25	96.00
sec_cm_bus_integrity				24	25	96.00
	rv_dm_tl_intg_err	70.000s	6567.488us	24	25	96.00
sec_cm_lc_hw_debug_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	48.000s	1186.419us	2	2	100.00
	rv_dm_debug_disabled	52.000s	65.771us	2	2	100.00
sec_cm_lc_dft_en_intersig_mubi				4	4	100.00
	rv_dm_sba_debug_disabled	48.000s	1186.419us	2	2	100.00
	rv_dm_debug_disabled	52.000s	65.771us	2	2	100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi				2	2	100.00
	rv_dm_smoke	57.000s	1897.131us	2	2	100.00
sec_cm_dm_en_ctrl_lc_gated				9	10	90.00
	rv_dm_buffered_enable	53.000s	591.006us	9	10	90.00
sec_cm_sba_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	50.000s	92.659us	4	4	100.00
sec_cm_mem_tl_lc_gate_fsm_sparse				4	4	100.00
	rv_dm_sparse_lc_gate_fsm	50.000s	92.659us	4	4	100.00
sec_cm_exec_ctrl_mubi				9	10	90.00
	rv_dm_buffered_enable	53.000s	591.006us	9	10	90.00

2/20 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				2	20	10.00
	rv_dm_stress_all_with_rand_reset	101.000s	4293.971us	2	20	10.00

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	rv_dm_scanmode	40.000s	0.583us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (tl_device_seq.sv:151) sequencer [m_tl_sba_device_seq] Cannot randomize rsp				37 test runs
	rv_dm_delayed_resp_sba_tl_access	6483615343978907104518808377528228588253385359706254005467282154100054153889	107	UVM_INFO @ 133603256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	101571230748573880081567956908440763629922005321013226741272995806193169623605	107	UVM_INFO @ 116751889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	84675122465209550310727621473023301522462954424395262900840849768741550710697	107	UVM_INFO @ 153276369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	14721306994288085370496879703618474520818293257578855867299535977558738940373	107	UVM_INFO @ 66137453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	9002373385396281370859259234942494872315506029272607855256920353163178541515	107	UVM_INFO @ 295132643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	66080203204936401547487690583765616610106319365398870752035213544986088901634	107	UVM_INFO @ 87342543 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	21475641457605048117049102625308605214128941217028901789903906551167946071653	152	UVM_INFO @ 4764794127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	52466635198068529488093777507172978344680190487913580611843555075159841604506	107	UVM_INFO @ 499339439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	39886587398192686932420931486306835471396214879895404381097647180399201175218	107	UVM_INFO @ 60865762 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	17504062790267093048387819779611921566088371087415568635846598164893643354646	107	UVM_INFO @ 169479501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	39556765965997142234658934730261341493790867229491013878792534056298878795837	107	UVM_INFO @ 62901997 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	91584327399882080085482502948648851920260700913093931121947842402231757453061	107	UVM_INFO @ 566583247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	77780462625745083115236905772466066424559153476281980582334139017109905225533	107	UVM_INFO @ 125236089 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	42164486290763678947486677620114620183911462279161940980882332123511364325411	107	UVM_INFO @ 947242931 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	101957914302258239971431259775687733025327057251190371758474085004948706512977	107	UVM_INFO @ 89296228 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	56810022115277338622446085851342744071112104354332413283061185021572626698639	107	UVM_INFO @ 50283701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	41627053750454096334382689539079645705484878780116884605030677614756082921651	107	UVM_INFO @ 143334992 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	84050639870968625377346222673294248655781085331068994707182277857621361108534	107	UVM_INFO @ 443773048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	93258582477977332191399969384475120223664360330777494084690278477702985661446	107	UVM_INFO @ 91287315 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	115770799844483901740847967306672377683509506159528810506690857487088054008412	107	UVM_INFO @ 139943840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	35631512917377646022565896152655962509403133909376251429248029723368907860895	107	UVM_INFO @ 205856535 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	22585976856228709761779982648598349143785742233734029863920211396222726404920	107	UVM_INFO @ 168135946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	89145576736919979793385447026081543896062151301216111282977584389089038107217	107	UVM_INFO @ 387606321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	86458915445416020456872227301060430650562509455497297279473536465455465429137	107	UVM_INFO @ 199970521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	99704998562226362158503092853965210825506547483755460662035896858382554595013	107	UVM_INFO @ 68322876 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	21838148586051330196060215159047038682739949647157451354864577810749821348098	107	UVM_INFO @ 124587504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	53889004512840429328445593767024795685014696459916859299456858331985395514923	107	UVM_INFO @ 724686083 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	26950992257099142428029288176617998513986129024596070916929898512974386298267	107	UVM_INFO @ 317774711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	22478431466867455361872205216769467615071270786165311816615660201006803754392	107	UVM_INFO @ 166997596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	32588058680785856650733184316649814813933520329673526509014143693285676730299	107	UVM_INFO @ 182619891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	90006325843042641068223384023764918372581015215741218352407630545803783779258	107	UVM_INFO @ 172195490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	69457061785684651991967984933253869676978153837912432052500406595191322826172	107	UVM_INFO @ 562203359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	110877658976198361491679352697996004923742692870482845717261722285514928046619	107	UVM_INFO @ 77573545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	40526508314901538052876302968222350903055499878908548760564643186703724983803	107	UVM_INFO @ 169027207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_delayed_resp_sba_tl_access	1941889969711833804524307037235351711265392199120695509457083989208867480253	107	UVM_INFO @ 449081080 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_bad_sba_tl_access	71824992565861183657736377519469320123500535045815621601396591075511542369889	107	UVM_INFO @ 1040510633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_autoincr_sba_tl_access	37804658130183635156087652335411225023447624127077932487769881589739558753592	107	UVM_INFO @ 94321120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:481) [scoreboard] sba_tl_access_q item uncompared:				35 test runs
	rv_dm_sba_tl_access	52352295431591512195489924230024391601706057357074227912573062348096229587471	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23907
	rv_dm_sba_tl_access	43079512879589459711489218409423303794031987664622123295622435696222356160443	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23848
	rv_dm_autoincr_sba_tl_access	60726856862860474928286674496318429679920220990373555690892069065537874290633	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23859
	rv_dm_sba_tl_access	13738372278593189754270784237951695931693764046773463584410624858087410109660	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23919
	rv_dm_bad_sba_tl_access	78066566596950881195030912731010730867320568552922108274603547904772091329861	93	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @10083
	rv_dm_autoincr_sba_tl_access	8530994746535586119268818474714457079529203438443396200450068035641364250479	129	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24944
	rv_dm_sba_tl_access	103749207485191383007006598271491279292756178380359541988088237583514190429103	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23875
	rv_dm_bad_sba_tl_access	46509504962990889058025983239774346233866131317677859194610611800195644545135	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23849
	rv_dm_sba_tl_access	101827558124687358502397197687621434199492525615760438799011229503618778403435	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23849
	rv_dm_sba_tl_access	57972644557785722773484694620814535310815905309533586892066263305509954676643	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23889
	rv_dm_autoincr_sba_tl_access	7525871388928659279151084377405033928401087902511700526451125791017842611212	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24025
	rv_dm_sba_tl_access	4039851966269053069616389643711859028031769926604267636628562046661878374038	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23836
	rv_dm_autoincr_sba_tl_access	41103889250050071310932544108818732147554105852755345690501301511326075300087	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24036
	rv_dm_sba_tl_access	87439356060337891087228623398145571180868450254280987062070098834241305270459	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23839
	rv_dm_sba_tl_access	60755018586805590969202865264970811539510524149373076325051454916544289925036	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23837
	rv_dm_bad_sba_tl_access	26517905591093021151392304156294847993229999721709218169637763073047560704273	108	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23978
	rv_dm_sba_tl_access	64689812368150378253158943110943565819326850824872410155652909618780477987073	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23901
	rv_dm_sba_tl_access	81714671803406910336768331152896138455642027320820268073321218822866941691796	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23836
	rv_dm_bad_sba_tl_access	1106365647035598444759111801049518537867369504613540437389380231459934304940	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23891
	rv_dm_sba_tl_access	103037575034295938313114446126382199385494322224870890041148509702928702569411	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23857
	rv_dm_bad_sba_tl_access	84315192193618344074924237115464297763693199476637083136947676220075056069386	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24291
	rv_dm_sba_tl_access	36846527854716929346625344230795683089871131559328331250188390850960608901364	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23911
	rv_dm_autoincr_sba_tl_access	20031672755171318476407218301280532563254312300620377905718293523595960659791	120	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24396
	rv_dm_sba_tl_access	107678193250966336794200398530233737422962633633056403322193124851279681347099	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23901
	rv_dm_sba_tl_access	41900586202621453886094141700013088545279140485949682705599194488553303261358	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23896
	rv_dm_autoincr_sba_tl_access	47948314621339712727578378405786168064217204133578077611515970924606496243651	111	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @26299
	rv_dm_sba_tl_access	95058018062328916545272074227580357877143820361215190039312573503271227755763	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23901
	rv_dm_autoincr_sba_tl_access	94807039098546066754090386815929857061194101968200960011414237309197424879818	99	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24226
	rv_dm_sba_tl_access	82845099682228097286376521644641298769968245545658121563553703742556598161726	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23902
	rv_dm_sba_tl_access	8299450388253278730957688199607551093778652200531685709475691269296874569	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23898
	rv_dm_bad_sba_tl_access	83478517097708867759779379833201829559402427665577148434683622325590472230767	102	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @24071
	rv_dm_sba_tl_access	67097566681324734571566998394004110731808770273229595936152428655131391890814	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23842
	rv_dm_bad_sba_tl_access	111747749299900947330939920046120798731595927846532998054225929331742658236676	96	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23925
	rv_dm_autoincr_sba_tl_access	36601628087468040971162190412976515689984794284445732768773767558492161868224	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23900
	rv_dm_sba_tl_access	74565562138677140305224078938450004065699682875937214175583206249961618250170	87	------------------------------------------------------------------- Name Type Size Value ------------------------------------------------------------------- req cip_tl_seq_item - @23920
UVM_ERROR (rv_dm_hart_unavail_vseq.sv:24) [rv_dm_hart_unavail_vseq] Check failed jtag_dmi_ral.dmstatus.anyunavail.get_mirrored_value() == req_unavailable (* [] vs [*])				13 test runs
	rv_dm_hart_unavail	44870108206824304049397977942225477656493626147748358565958927411088853652770	87	UVM_INFO @ 207625889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	37126408077319437746091769654089404449552755765809583286133935168456551283365	87	UVM_INFO @ 110664259 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	109820498384218845502915281403365956615766148608232530489859579614621751467076	87	UVM_INFO @ 94108585 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	11305516253437371840060684124171544731823895172283081825600016546435283907261	87	UVM_INFO @ 64151162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	62411717166204273706710334266951720542242458838317345342460063436484044545023	102	UVM_INFO @ 433772592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_hart_unavail	70744191831708213130015130332927792636538623583017458487435905700989055204406	87	UVM_INFO @ 264179358 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	64974769813214400611400849586071622090308108797586463695885138120177580974558	94	UVM_INFO @ 5745915941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	54289715964773505963265876102789551501258295845237589086453316462047130405781	88	UVM_INFO @ 198954432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	30566177672983587073194915456328166256285416431896944093979701979211696583862	88	UVM_INFO @ 110978173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	96513774542456847382077226703449319002011752280932256093774498465033682673475	94	UVM_INFO @ 2573587759 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	36604375500574330008947302053037741692367113041743890583335205608723211075009	103	UVM_INFO @ 243034982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	84348958858748680018178834071634045058454220598549504396617924636089467975172	88	UVM_INFO @ 323888119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	66836963026740626320590309219946225193674633844752358745787549800748587596904	98	UVM_INFO @ 124021788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_jtag_dmi_debug_disabled_vseq.sv:16) [rv_dm_jtag_dmi_debug_disabled_vseq] Check failed rdata == expected_value (* [] vs [*])				11 test runs
	rv_dm_jtag_dmi_debug_disabled	54104701803077659075506083626766610426158128733943544262947160980590451545403	87	UVM_INFO @ 106387337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_jtag_dmi_debug_disabled	6674983495769276131708121389034866261294001323414580639181539355214152121674	87	UVM_INFO @ 227512910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	66846274435754913173163853632394719682956433647325876714104934889558126892595	90	UVM_INFO @ 1240767026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	104431605323444300385461205099394454309477795464644132958485642209019644568308	91	UVM_INFO @ 168848559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	3092225817533846464001629519307693088090863094845607218610159466305840313110	89	UVM_INFO @ 870516731 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	69090283872550946510647742389507328417004674828604786612224670937125713861671	94	UVM_INFO @ 1707785750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	6367958276204372789571855925114613345611566637615066858737853311808593509284	92	UVM_INFO @ 325880408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	71986893784854464589174615693204110804656505409167348963411287735870448457877	131	UVM_INFO @ 2592421714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	32341712377952332100899708308633185920100461235022880369970645126716301179544	93	UVM_INFO @ 1282848174 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	12772413859228937562649823254944527634666029406148788334680341570351548568931	143	UVM_INFO @ 6325649913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	54452595872570408404224102026132413124907540941026617575441539668562011119177	88	UVM_INFO @ 514539360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_mem_tl_access_resuming_vseq.sv:56) [rv_dm_mem_tl_access_resuming_vseq] Check failed jtag_dmi_ral.dmstatus.anyhalted.get_mirrored_value() == 'b (* [] vs [*])				8 test runs
	rv_dm_mem_tl_access_resuming	40920179065507512721736572600856882259837821369762204631334829409177063987380	87	UVM_INFO @ 269608705 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_mem_tl_access_resuming	2895576085118563614969231606833076342621401835665813785493759182959694564575	87	UVM_INFO @ 61065857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	53024472909631952297162421666370750561317641074337266340446174123903787746419	88	UVM_INFO @ 134237070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	110260326372334276588013202833703191199496188998625631548972345624007867972948	98	UVM_INFO @ 178110971 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	108055247040611271064385969295249155940159313661183437778565678151424647003271	88	UVM_INFO @ 173397832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	76330559565965256905451651142718512799428186092893831277120095802788203195173	89	UVM_INFO @ 1361223994 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	49012742821570750868170113297304173276779583028672043764348546454479153987458	93	UVM_INFO @ 346617649 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	72721649643530486551455388767601189338678288056406441297098546850162842045330	89	UVM_INFO @ 1723070989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1230) [rv_dm_common_vseq] Check failed (vseq_done)				8 test runs
	rv_dm_stress_all_with_rand_reset	104936014494105217130472728162877204547038265663556485507284970210865092361089	111	UVM_INFO @ 1604868884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	34288139408555514142633761257243764195682147053978920867067909261795172266645	143	UVM_INFO @ 3262100838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	107719924220882510297874492864574987171366252976784868120014854038661552895361	149	UVM_INFO @ 4293970965 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	93332245718146916031927474848489537515868172502232872873839962961688668817230	97	UVM_INFO @ 696044121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	70776315948641487396573359900117151501614958346072217708479682776846430784923	94	UVM_INFO @ 311631180 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	102813975133640118749877058087710675847097081757415703028428032053391478184644	105	UVM_INFO @ 168424638 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	81366125477578182011214624982827756953672145259753030075719583544853751311134	100	UVM_INFO @ 2251347832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all_with_rand_reset	94266996549940643021827202706763357420668391961557806728708463018386985040315	116	UVM_INFO @ 1228074040 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				4 test runs
	rv_dm_stress_all	87151291892795978737085277043263763810131652899075459809144323607340553137740	None
	rv_dm_stress_all	57915039349878073480783022733656502563251486931978743522637453351467121670407	None
	rv_dm_stress_all	32018646360156722509464184548036059585399819000207615549712433483310002667210	None
	rv_dm_stress_all	34552444877620251344567619858095765362225139153599414820407873362775976390256	None
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue				3 test runs
	rv_dm_stress_all	60055711788607687411164149063304750352445688706408808276228142620997101623815	89	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	33447464339592475349615288400966343825992841467029411952154311909178397969455	88	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_dm_stress_all	84865582561650213841018836575822453704341765251779443230547782630890869658925	90	UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23890) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	35644176919338151634654910336794918700721747996479942375219103487599955866245	87	). UVM_INFO @ 33083269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
xmsim: E,ASRTST (/nightly/current_run/scratch/master/rv_dm-sim-xcelium/default/fusesoc-work/src/lowrisc_tlul_common_/rtl/tlul_assert.sv,381): Assertion aKnown_AKnownEnable has failed				1 test run
	rv_dm_scanmode	78498713969073692563677830213498320170384506994758357884619026467394152201613	87	UVM_ERROR @ 583186 ps: (tlul_assert.sv:381) [ASSERT FAILED] aKnown_AKnownEnable UVM_INFO @ 583186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_scoreboard.sv:409) scoreboard [scoreboard] Unexpected response to read from address * in mem reg block. Problems: '{"Expected read d_data=, but it was "}. Item: (req: (cip_tl_seq_item@23892) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * }				1 test run
	rv_dm_rom_read_access	25885708336664395325209327553066187455258697300885814757455760674660744289339	87	). UVM_INFO @ 66607236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_dm_buffered_enable_vseq.sv:164) [rv_dm_buffered_enable_vseq] Check failed saw_a_valid == tgt_copy == Sba (* [] vs [*])				1 test run
	rv_dm_buffered_enable	46537480715365066622919238439221352091374728051912443160567255607377722388226	92	UVM_INFO @ 119362277 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [rv_dm_common_vseq] Expected alert (fatal_fault) did not fire in * cycles.				1 test run
	rv_dm_tl_intg_err	95493769988551096629031814123083076809525965914906550136872446603864722543066	311	UVM_INFO @ 4334351051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---