Simulation Results: rv_timer

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.97 %
  • code
  • 90.45 %
  • assert
  • 97.47 %
  • func
  • 100.00 %
  • block
  • 99.10 %
  • line
  • 99.02 %
  • branch
  • 99.26 %
  • toggle
  • 73.08 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
55.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 20 20 100.00
rv_timer_random 3.000s 1846.596us 20 20 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 1.000s 56.176us 1 1 100.00
csr_rw 5 5 100.00
rv_timer_csr_rw 2.000s 31.990us 5 5 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 5.000s 559.448us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 1.000s 17.335us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rv_timer_csr_mem_rw_with_rand_reset 2.000s 14.227us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rv_timer_csr_rw 2.000s 31.990us 5 5 100.00
rv_timer_csr_aliasing 1.000s 17.335us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 20 20 100.00
rv_timer_random_reset 7.000s 8910.359us 20 20 100.00
disabled 20 20 100.00
rv_timer_disabled 7.000s 3418.532us 20 20 100.00
cfg_update_on_fly 10 10 100.00
rv_timer_cfg_update_on_fly 424.000s 344619.499us 10 10 100.00
no_interrupt_test 10 10 100.00
rv_timer_cfg_update_on_fly 424.000s 344619.499us 10 10 100.00
stress 20 20 100.00
rv_timer_stress_all 12.000s 6509.839us 20 20 100.00
alert_test 10 10 100.00
rv_timer_alert_test 2.000s 17.171us 10 10 100.00
intr_test 10 10 100.00
rv_timer_intr_test 2.000s 18.699us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rv_timer_tl_errors 3.000s 192.584us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rv_timer_tl_errors 3.000s 192.584us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 56.176us 1 1 100.00
rv_timer_csr_rw 2.000s 31.990us 5 5 100.00
rv_timer_csr_aliasing 1.000s 17.335us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 66.768us 5 5 100.00
tl_d_partial_access 12 12 100.00
rv_timer_csr_hw_reset 1.000s 56.176us 1 1 100.00
rv_timer_csr_rw 2.000s 31.990us 5 5 100.00
rv_timer_csr_aliasing 1.000s 17.335us 1 1 100.00
rv_timer_same_csr_outstanding 1.000s 66.768us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rv_timer_sec_cm 2.000s 62.680us 5 5 100.00
rv_timer_tl_intg_err 2.000s 289.708us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
rv_timer_tl_intg_err 2.000s 289.708us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 2 10 20.00
rv_timer_min 2.000s 55.619us 2 10 20.00
max_value 0 10 0.00
rv_timer_max 3.000s 132.849us 0 10 0.00
stress_all_with_rand_reset 20 20 100.00
rv_timer_stress_all_with_rand_reset 60.000s 20928.510us 20 20 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:227) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 9 test runs
rv_timer_max 30326929804600614667776611419450564828930370201007476975014041493850729394978 85
UVM_INFO @ 910421082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 86729046791784476075903497982768782874591123810471270549994574390547412898267 86
UVM_INFO @ 132848913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 81307912138897927445947533822404468892714330857455176906657283181792690277433 84
UVM_INFO @ 45372529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 80593171742292450576109170080587236467897357227333577291878498781083777848993 84
UVM_INFO @ 163228719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 92379772318311749809158761437916761733699963394545283418141285699073880410320 84
UVM_INFO @ 43021583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 40377473385640517547243730052946895103997409886542723083159598742956902027245 84
UVM_INFO @ 146016964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 53990382518792518499986314634358961892058109468562782758665747514299311515146 84
UVM_INFO @ 86935171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 112040754358709985324705948379080591484436206589999226182549983761378294742360 84
UVM_INFO @ 54167618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_max 114462522914547494710000424002706433962421167924102753486047716508724398732500 84
UVM_INFO @ 181138864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:183) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 8 test runs
rv_timer_min 4771926596812214690308531374532879960984733243385828773600379322808282435671 85
UVM_INFO @ 55619182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 53588446779918974600403531537019395552984208817469575158025237416361798060635 84
UVM_INFO @ 62086824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 41903859122614945127418117362845118451911521444896391187767258269631943980860 84
UVM_INFO @ 83744553 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 53302419727650149997324338861075772406811198096466214362997726491782934398432 84
UVM_INFO @ 80359466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 104326400456394152538174503078878176582707960018670728457433073395489271905465 84
UVM_INFO @ 653926902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 38456775568507579972661993781138974600898252675835721813544786721038501765262 84
UVM_INFO @ 107756798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 76587877353877282539904409652383620287360331509891034672783968018163788638392 84
UVM_INFO @ 115608645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_min 72114635127092560496270609321396672348528480808871523223691400595731753279699 86
UVM_INFO @ 67962311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:343) [scoreboard] Check failed cfg.intr_vif.sample_pin(.idx(intr_pin_idx)) === (stored_intr_status_exp[i][j] & stored_en_interrupt[i][j]) (* [*] vs * [*]) 1 test run
rv_timer_max 108925571923780013166296981843129196943147534324284630538710531120176365603201 84
UVM_INFO @ 84483961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---