Simulation Results: spi_host

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.96 %
  • code
  • 91.32 %
  • assert
  • 96.79 %
  • func
  • 90.76 %
  • block
  • 97.01 %
  • line
  • 98.76 %
  • branch
  • 93.45 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
spi_host_smoke 84.000s 2958.632us 10 10 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 22.340us 1 1 100.00
csr_rw 5 5 100.00
spi_host_csr_rw 2.000s 20.168us 5 5 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 456.615us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 18.656us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 109.629us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
spi_host_csr_rw 2.000s 20.168us 5 5 100.00
spi_host_csr_aliasing 1.000s 18.656us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 2.000s 38.743us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 18.861us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 10 10 100.00
spi_host_performance 2.000s 61.471us 10 10 100.00
error_event_intr 30 30 100.00
spi_host_overflow_underflow 4.000s 377.564us 10 10 100.00
spi_host_error_cmd 2.000s 26.773us 10 10 100.00
spi_host_event 21.000s 2286.837us 10 10 100.00
clock_rate 10 10 100.00
spi_host_speed 8.000s 146.669us 10 10 100.00
speed 10 10 100.00
spi_host_speed 8.000s 146.669us 10 10 100.00
chip_select_timing 10 10 100.00
spi_host_speed 8.000s 146.669us 10 10 100.00
upper_range_clkdiv 5 5 100.00
spi_host_upper_range_clkdiv 500.000s 42769.796us 5 5 100.00
sw_reset 10 10 100.00
spi_host_sw_reset 27.000s 2146.763us 10 10 100.00
passthrough_mode 10 10 100.00
spi_host_passthrough_mode 2.000s 111.381us 10 10 100.00
cpol_cpha 10 10 100.00
spi_host_speed 8.000s 146.669us 10 10 100.00
full_cycle 10 10 100.00
spi_host_speed 8.000s 146.669us 10 10 100.00
duplex 10 10 100.00
spi_host_smoke 84.000s 2958.632us 10 10 100.00
tx_rx_only 10 10 100.00
spi_host_smoke 84.000s 2958.632us 10 10 100.00
stress_all 10 10 100.00
spi_host_stress_all 47.000s 5384.854us 10 10 100.00
spien 10 10 100.00
spi_host_spien 92.000s 9118.485us 10 10 100.00
stall 10 10 100.00
spi_host_status_stall 309.000s 104012.768us 10 10 100.00
Idlecsbactive 10 10 100.00
spi_host_idlecsbactive 8.000s 421.553us 10 10 100.00
data_fifo_status 10 10 100.00
spi_host_overflow_underflow 4.000s 377.564us 10 10 100.00
alert_test 10 10 100.00
spi_host_alert_test 2.000s 42.949us 10 10 100.00
intr_test 10 10 100.00
spi_host_intr_test 2.000s 37.795us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
spi_host_tl_errors 4.000s 624.400us 25 25 100.00
tl_d_illegal_access 25 25 100.00
spi_host_tl_errors 4.000s 624.400us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 22.340us 1 1 100.00
spi_host_csr_rw 2.000s 20.168us 5 5 100.00
spi_host_csr_aliasing 1.000s 18.656us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 16.915us 5 5 100.00
tl_d_partial_access 12 12 100.00
spi_host_csr_hw_reset 2.000s 22.340us 1 1 100.00
spi_host_csr_rw 2.000s 20.168us 5 5 100.00
spi_host_csr_aliasing 1.000s 18.656us 1 1 100.00
spi_host_same_csr_outstanding 2.000s 16.915us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
spi_host_tl_intg_err 3.000s 717.882us 25 25 100.00
spi_host_sec_cm 2.000s 67.939us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
spi_host_tl_intg_err 3.000s 717.882us 25 25 100.00