| V1 |
|
97.30% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 6.000s | 2930.949us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 46.716us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 22.557us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 5.000s | 584.674us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 5.000s | 16.025us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 4 | 5 | 80.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 10.000s | 10005.661us | 4 | 5 | 80.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 22.557us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 5.000s | 16.025us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 354.000s | 101126.707us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 148.000s | 83232.464us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 38.000s | 6589.765us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 242.000s | 5275.173us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 211.000s | 174611.074us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 60.000s | 10663.801us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 67.000s | 15508.144us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 69.000s | 76953.091us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 6.000s | 3729.071us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 362.000s | 23003.704us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 8.000s | 6673.448us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 8.000s | 7381.790us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 8.000s | 2768.832us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 27.000s | 35294.224us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 4.000s | 6726.074us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 6.000s | 2930.949us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 6.000s | 3729.071us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 60.000s | 10663.801us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 714.000s | 229053.461us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 6.000s | 14.698us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 319.410us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 6.000s | 319.410us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 46.716us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 22.557us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 5.000s | 16.025us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 55.153us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 46.716us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 22.557us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 5.000s | 16.025us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 55.153us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 45.000s | 7361.637us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 813.996us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 3.000s | 376.670us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 813.996us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 3.000s | 376.670us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 27.000s | 35294.224us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 27.000s | 35294.224us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 22.557us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 69.000s | 76953.091us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 69.000s | 76953.091us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 69.000s | 76953.091us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 67.000s | 15508.144us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3602.064s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 45.000s | 7361.637us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 6.000s | 2930.949us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 6.000s | 2930.949us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 69.000s | 76953.091us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 813.996us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 67.000s | 15508.144us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 813.996us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 813.996us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 6.000s | 2930.949us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 813.996us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 51.000s | 1357.339us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 25028026943727507198074183037041202921464567494510900197393558266676806230278 | None | ||
| sram_ctrl_mubi_enc_err | 33273683136885092020522473547379868998561015991458890046726657006088294803976 | None | ||
| sram_ctrl_readback_err | 86463835657212872579061081751789923994162740401701972358162663044086292041098 | None | ||
| sram_ctrl_mubi_enc_err | 3078058561378637985128736510561581062752436766643506583930284664142491702168 | None | ||
| sram_ctrl_readback_err | 17686130902081807471492128810476973537461957129069913778501738469082709147555 | None | ||
| sram_ctrl_mubi_enc_err | 41424131293933422030800652211585146536066249485459308496153302437797845117848 | None | ||
| sram_ctrl_readback_err | 29367544272745226872336794718057333794248551483892193454489421848891545553659 | None | ||
| sram_ctrl_mubi_enc_err | 87199480352783823161641255231666536377235552186436303135865029362072289919843 | None | ||
| sram_ctrl_readback_err | 95885794438677987230838523447796680908414296722484914171973462599338821804699 | None | ||
| sram_ctrl_mubi_enc_err | 95253589800844998486553415950876559289977242485763523632557107247276669283756 | None | ||
| sram_ctrl_readback_err | 87177343857569093058215752882501524215234243007241672742745174230660536985106 | None | ||
| sram_ctrl_mubi_enc_err | 89548809392082033935967305840199120194203077767094719385677055989477970452261 | None | ||
| sram_ctrl_readback_err | 17967912640109527699211139513718014184802259373757543677331902762224312875930 | None | ||
| sram_ctrl_mubi_enc_err | 79355735776312517498180211481571344009470533452837569158881941676117006815369 | None | ||
| sram_ctrl_readback_err | 86874482620377572390675838358492538566393418706843307528092242746872021400923 | None | ||
| sram_ctrl_mubi_enc_err | 9367556934092222240875740837672253328674531656128751610502108409659698180554 | None | ||
| UVM_FATAL (sram_ctrl_base_vseq.sv:177) [sram_ctrl_common_vseq] Timed out waiting for initialization done | 1 test run | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 82393310813317184584445462115500631094819855506548408246342955855659804840966 | 85 |
UVM_INFO @ 10005660509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|