| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
81.82% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 595.150us | 8 | 8 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 20.502us | 1 | 1 | 100.00 | |
| csr_rw | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 42.919us | 5 | 5 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_bit_bash | 4.000s | 760.907us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| sram_ctrl_csr_aliasing | 1.000s | 14.064us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_mem_rw_with_rand_reset | 7.000s | 118.983us | 5 | 5 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 6 | 6 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 42.919us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 14.064us | 1 | 1 | 100.00 | |
| mem_walk | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_walk | 12.000s | 814.683us | 8 | 8 | 100.00 | |
| mem_partial_access | 8 | 8 | 100.00 | |||
| sram_ctrl_mem_partial_access | 6.000s | 771.368us | 8 | 8 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| multiple_keys | 8 | 8 | 100.00 | |||
| sram_ctrl_multiple_keys | 14.000s | 2076.376us | 8 | 8 | 100.00 | |
| stress_pipeline | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_pipeline | 228.000s | 29786.451us | 8 | 8 | 100.00 | |
| bijection | 8 | 8 | 100.00 | |||
| sram_ctrl_bijection | 14.000s | 974.399us | 8 | 8 | 100.00 | |
| access_during_key_req | 8 | 8 | 100.00 | |||
| sram_ctrl_access_during_key_req | 21.000s | 2334.086us | 8 | 8 | 100.00 | |
| lc_escalation | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 9.000s | 2224.273us | 8 | 8 | 100.00 | |
| executable | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 7152.301us | 8 | 8 | 100.00 | |
| partial_access | 16 | 16 | 100.00 | |||
| sram_ctrl_partial_access | 3.000s | 33.886us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access_b2b | 462.000s | 97102.392us | 8 | 8 | 100.00 | |
| max_throughput | 24 | 24 | 100.00 | |||
| sram_ctrl_max_throughput | 2.000s | 76.212us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_partial_write | 2.000s | 74.115us | 8 | 8 | 100.00 | |
| sram_ctrl_throughput_w_readback | 3.000s | 93.299us | 8 | 8 | 100.00 | |
| regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 14.000s | 4162.363us | 8 | 8 | 100.00 | |
| ram_cfg | 8 | 8 | 100.00 | |||
| sram_ctrl_ram_cfg | 2.000s | 26.167us | 8 | 8 | 100.00 | |
| non_pow2_mem_size | 24 | 24 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 595.150us | 8 | 8 | 100.00 | |
| sram_ctrl_partial_access | 3.000s | 33.886us | 8 | 8 | 100.00 | |
| sram_ctrl_access_during_key_req | 21.000s | 2334.086us | 8 | 8 | 100.00 | |
| stress_all | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all | 54.000s | 6717.377us | 8 | 8 | 100.00 | |
| alert_test | 10 | 10 | 100.00 | |||
| sram_ctrl_alert_test | 7.000s | 14.758us | 10 | 10 | 100.00 | |
| tl_d_oob_addr_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 411.350us | 25 | 25 | 100.00 | |
| tl_d_illegal_access | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_errors | 5.000s | 411.350us | 25 | 25 | 100.00 | |
| tl_d_outstanding_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 20.502us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 42.919us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 14.064us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 49.545us | 5 | 5 | 100.00 | |
| tl_d_partial_access | 12 | 12 | 100.00 | |||
| sram_ctrl_csr_hw_reset | 2.000s | 20.502us | 1 | 1 | 100.00 | |
| sram_ctrl_csr_rw | 2.000s | 42.919us | 5 | 5 | 100.00 | |
| sram_ctrl_csr_aliasing | 1.000s | 14.064us | 1 | 1 | 100.00 | |
| sram_ctrl_same_csr_outstanding | 2.000s | 49.545us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| passthru_mem_tl_intg_err | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 1514.776us | 5 | 5 | 100.00 | |
| tl_intg_err | 30 | 30 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 797.636us | 5 | 5 | 100.00 | |
| sram_ctrl_tl_intg_err | 3.000s | 378.191us | 25 | 25 | 100.00 | |
| prim_count_check | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 797.636us | 5 | 5 | 100.00 | |
| sec_cm_bus_integrity | 25 | 25 | 100.00 | |||
| sram_ctrl_tl_intg_err | 3.000s | 378.191us | 25 | 25 | 100.00 | |
| sec_cm_ctrl_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 14.000s | 4162.363us | 8 | 8 | 100.00 | |
| sec_cm_readback_config_regwen | 8 | 8 | 100.00 | |||
| sram_ctrl_regwen | 14.000s | 4162.363us | 8 | 8 | 100.00 | |
| sec_cm_exec_config_regwen | 5 | 5 | 100.00 | |||
| sram_ctrl_csr_rw | 2.000s | 42.919us | 5 | 5 | 100.00 | |
| sec_cm_exec_config_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 7152.301us | 8 | 8 | 100.00 | |
| sec_cm_exec_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 7152.301us | 8 | 8 | 100.00 | |
| sec_cm_lc_hw_debug_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 7152.301us | 8 | 8 | 100.00 | |
| sec_cm_lc_escalate_en_intersig_mubi | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 9.000s | 2224.273us | 8 | 8 | 100.00 | |
| sec_cm_prim_ram_ctrl_mubi | 0 | 8 | 0.00 | |||
| sram_ctrl_mubi_enc_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_integrity | 5 | 5 | 100.00 | |||
| sram_ctrl_passthru_mem_tl_intg_err | 4.000s | 1514.776us | 5 | 5 | 100.00 | |
| sec_cm_mem_readback | 0 | 8 | 0.00 | |||
| sram_ctrl_readback_err | 3601.000s | 0.000us | 0 | 8 | 0.00 | |
| sec_cm_mem_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 595.150us | 8 | 8 | 100.00 | |
| sec_cm_addr_scramble | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 595.150us | 8 | 8 | 100.00 | |
| sec_cm_instr_bus_lc_gated | 8 | 8 | 100.00 | |||
| sram_ctrl_executable | 14.000s | 7152.301us | 8 | 8 | 100.00 | |
| sec_cm_ram_tl_lc_gate_fsm_sparse | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 797.636us | 5 | 5 | 100.00 | |
| sec_cm_key_global_esc | 8 | 8 | 100.00 | |||
| sram_ctrl_lc_escalation | 9.000s | 2224.273us | 8 | 8 | 100.00 | |
| sec_cm_key_local_esc | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 797.636us | 5 | 5 | 100.00 | |
| sec_cm_init_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 797.636us | 5 | 5 | 100.00 | |
| sec_cm_scramble_key_sideload | 8 | 8 | 100.00 | |||
| sram_ctrl_smoke | 2.000s | 595.150us | 8 | 8 | 100.00 | |
| sec_cm_tlul_fifo_ctr_redun | 5 | 5 | 100.00 | |||
| sram_ctrl_sec_cm | 5.000s | 797.636us | 5 | 5 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 8 | 8 | 100.00 | |||
| sram_ctrl_stress_all_with_rand_reset | 104.000s | 9554.158us | 8 | 8 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Job timed out after * minutes | 16 test runs | |||
| sram_ctrl_readback_err | 101716718101261742207324690137016510669764084778033825890055823865289277964009 | None | ||
| sram_ctrl_mubi_enc_err | 29088288040353149427535639675353276867694434822901380690884441235226088481455 | None | ||
| sram_ctrl_readback_err | 103077853536370703327734945311199253451171496892295472755169640194192101062125 | None | ||
| sram_ctrl_mubi_enc_err | 50990000648641513178704759160824751435966235563508723936928640119158263423070 | None | ||
| sram_ctrl_readback_err | 103699413150600773701383554081572631819264496096998206320629968315709087061690 | None | ||
| sram_ctrl_mubi_enc_err | 3629929002216390140998605363321848387630082221703108326075828364589121200596 | None | ||
| sram_ctrl_readback_err | 20724696587095039645513176380063957438482952011952723437794716290088516460770 | None | ||
| sram_ctrl_mubi_enc_err | 52377750727582496964454791205572336330796429645918552854384488601240029506692 | None | ||
| sram_ctrl_readback_err | 2696285848868668990520675146132368821340810395674017644742080114665301401235 | None | ||
| sram_ctrl_mubi_enc_err | 111101925696095853579206836302202686906537933756794332865985009387940116565650 | None | ||
| sram_ctrl_readback_err | 108062605340063147971699164305394115390418242458517842966244013407979974500132 | None | ||
| sram_ctrl_mubi_enc_err | 77761990097617545264863837347581202519947631989575908495520278796374236786987 | None | ||
| sram_ctrl_readback_err | 96341526531658078550648550597933023605166924776646666975435198349181156320974 | None | ||
| sram_ctrl_mubi_enc_err | 22399374414929429098641969068620026040722108500144300422170803496352703870853 | None | ||
| sram_ctrl_readback_err | 14135521000821774837318082700557880874151627909649185287205081563308118066590 | None | ||
| sram_ctrl_mubi_enc_err | 64041799944242906461190387428438093553244412632914072011072154381785166208017 | None | ||