Simulation Results: uart

 
11/09/2026 15:01:27 DVSim: v1.49.0 sha: 55d8d87 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.52 %
  • code
  • 92.73 %
  • assert
  • 97.12 %
  • func
  • 90.69 %
  • block
  • 99.08 %
  • line
  • 99.52 %
  • branch
  • 98.34 %
  • toggle
  • 73.08 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.47%
V2S
100.00%
V3
90.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
uart_smoke 25.000s 5908.121us 10 10 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 1.000s 14.155us 1 1 100.00
csr_rw 5 5 100.00
uart_csr_rw 2.000s 13.104us 5 5 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 3.000s 827.640us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.000s 14.334us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
uart_csr_mem_rw_with_rand_reset 2.000s 36.292us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
uart_csr_rw 2.000s 13.104us 5 5 100.00
uart_csr_aliasing 1.000s 14.334us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 10 10 100.00
uart_tx_rx 308.000s 88269.071us 10 10 100.00
parity 20 20 100.00
uart_smoke 25.000s 5908.121us 10 10 100.00
uart_tx_rx 308.000s 88269.071us 10 10 100.00
parity_error 20 20 100.00
uart_intr 129.000s 59177.398us 10 10 100.00
uart_rx_parity_err 329.000s 139003.571us 10 10 100.00
watermark 20 20 100.00
uart_tx_rx 308.000s 88269.071us 10 10 100.00
uart_intr 129.000s 59177.398us 10 10 100.00
fifo_full 10 10 100.00
uart_fifo_full 322.000s 125042.087us 10 10 100.00
fifo_overflow 10 10 100.00
uart_fifo_overflow 105.000s 123447.245us 10 10 100.00
fifo_reset 200 200 100.00
uart_fifo_reset 559.000s 168023.278us 200 200 100.00
rx_frame_err 10 10 100.00
uart_intr 129.000s 59177.398us 10 10 100.00
rx_break_err 10 10 100.00
uart_intr 129.000s 59177.398us 10 10 100.00
rx_timeout 10 10 100.00
uart_intr 129.000s 59177.398us 10 10 100.00
perf 10 10 100.00
uart_perf 554.000s 18484.307us 10 10 100.00
sys_loopback 10 10 100.00
uart_loopback 18.000s 10282.165us 10 10 100.00
line_loopback 10 10 100.00
uart_loopback 18.000s 10282.165us 10 10 100.00
rx_noise_filter 2 10 20.00
uart_noise_filter 230.000s 101816.643us 2 10 20.00
rx_start_bit_filter 10 10 100.00
uart_rx_start_bit_filter 56.000s 30210.404us 10 10 100.00
tx_overide 10 10 100.00
uart_tx_ovrd 21.000s 6685.044us 10 10 100.00
rx_oversample 10 10 100.00
uart_rx_oversample 53.000s 7322.634us 10 10 100.00
long_b2b_transfer 10 10 100.00
uart_long_xfer_wo_dly 938.000s 99300.714us 10 10 100.00
stress_all 4 10 40.00
uart_stress_all 1292.000s 164155.890us 4 10 40.00
alert_test 10 10 100.00
uart_alert_test 2.000s 50.071us 10 10 100.00
intr_test 10 10 100.00
uart_intr_test 2.000s 17.703us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
uart_tl_errors 3.000s 103.359us 25 25 100.00
tl_d_illegal_access 25 25 100.00
uart_tl_errors 3.000s 103.359us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
uart_csr_hw_reset 1.000s 14.155us 1 1 100.00
uart_csr_rw 2.000s 13.104us 5 5 100.00
uart_csr_aliasing 1.000s 14.334us 1 1 100.00
uart_same_csr_outstanding 2.000s 22.635us 5 5 100.00
tl_d_partial_access 12 12 100.00
uart_csr_hw_reset 1.000s 14.155us 1 1 100.00
uart_csr_rw 2.000s 13.104us 5 5 100.00
uart_csr_aliasing 1.000s 14.334us 1 1 100.00
uart_same_csr_outstanding 2.000s 22.635us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
uart_sec_cm 2.000s 69.877us 5 5 100.00
uart_tl_intg_err 2.000s 414.043us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
uart_tl_intg_err 2.000s 414.043us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 18 20 90.00
uart_stress_all_with_rand_reset 80.000s 25472.052us 18 20 90.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:392) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * 6 test runs
uart_stress_all 63712744974225673869355149531334012724101694618052253743791017164490247385619 96
UVM_ERROR @ 132804574092 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 132807313763 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 132809397163 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 132809459665 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 29811623829967930348686916389926052506826681210125777678533656065477553175823 104
UVM_ERROR @ 198304465826 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 198305159698 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 198305812754 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 198306476014 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 46466325737433631439504329086662736501375112658238906136576124857402305544092 84
UVM_ERROR @ 583457192 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 626516360 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
UVM_ERROR @ 626516360 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 626594792 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (1 [0x1] vs 0 [0x0]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 1
uart_stress_all 65978530181401826147390386585068391550913308603042082582780488034825919064649 84
UVM_ERROR @ 101090153 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 109040153 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 112300153 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 113850153 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_stress_all 106888134034026783702919551699368033443585276673960741223302396527801843351518 84
UVM_ERROR @ 17666962 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 38129921 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 38151427 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 38162180 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_noise_filter 34471110389665996227401580544804434795336956810018481442785557190329607015494 83
UVM_ERROR @ 4436090 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5123612 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 5811134 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 6498656 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:499) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: * 5 test runs
uart_stress_all 5283606421711180794726880380691292566593809622012539854695919083852353329276 173
UVM_ERROR @ 146373335540 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 146373720155 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (172 [0xac] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 146618566064 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 146618719910 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_noise_filter 76435854032759361870409591474059463386109930687219970534980056601386867402711 84
UVM_ERROR @ 506761007 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 506771424 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 253 [0xfd]) reg name: uart_reg_block.rdata
UVM_ERROR @ 506792258 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 506802675 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 254 [0xfe]) reg name: uart_reg_block.rdata
uart_noise_filter 60077201643504389616265369534722972799005049257296621979321723562568796984261 86
UVM_ERROR @ 6792313925 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 6792364945 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 247 [0xf7]) reg name: uart_reg_block.rdata
UVM_ERROR @ 6943241289 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 6943261697 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
uart_noise_filter 17146763284915152907745147032948581435917505302814754692174607504171799483056 83
UVM_ERROR @ 80538899 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 80632652 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 80653486 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 80757656 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 221 [0xdd]) reg name: uart_reg_block.rdata
uart_stress_all_with_rand_reset 47970029257926788398555460115600874429307446963261163090448204390418678470842 86
UVM_ERROR @ 103542708 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 103751043 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 252418899 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 252418899 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR (uart_scoreboard.sv:376) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 4 test runs
uart_noise_filter 24061159072642764003525685901913880294066824292382169417521157729957332534165 83
UVM_ERROR @ 51635921 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 51635921 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 100009610 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxParityErr
UVM_ERROR @ 100009610 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxParityErr
uart_stress_all 81926575414601371563566638313191029892449258925019970098635237756424541662322 96
UVM_ERROR @ 11345169982 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 11350889982 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 11351969982 ps: (uart_scoreboard.sv:376) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 11351969982 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
uart_noise_filter 30416262287902408279239562458839658002208600630145068267009273246558219065756 84
UVM_ERROR @ 19442826849 ps: (uart_scoreboard.sv:392) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 19442826849 ps: (csr_utils_pkg.sv:463) [csr_utils_pkg::csr_rd_check.isolation_fork.unmblk1] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 20003206332 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 7, clk_pulses: 0
UVM_ERROR @ 20003414667 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (241 [0xf1] vs 255 [0xff]) reg name: uart_reg_block.rdata
uart_noise_filter 5470877713763515807658163343767757184042966544277377576969149605863671865219 99
UVM_ERROR @ 101565532545 ps: (uart_scoreboard.sv:499) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 1 (+/-1), act: 9, clk_pulses: 0
UVM_ERROR @ 101565607011 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (70 [0x46] vs 191 [0xbf]) reg name: uart_reg_block.rdata
UVM_ERROR @ 101565628287 ps: (uart_scoreboard.sv:459) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 101565681477 ps: (uart_scoreboard.sv:529) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (70 [0x46] vs 106 [0x6a]) reg name: uart_reg_block.rdata
UVM_ERROR (uart_scoreboard.sv:443) [scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (* [*] vs * [*]) Interrupt: RxFrameErr 1 test run
uart_stress_all_with_rand_reset 103096526716469742576132771201996178635537138864465611495559833224654654199365 135
UVM_ERROR @ 1543425142 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr
UVM_INFO @ 1565155142 ps: (cip_base_vseq__tl_errors.svh:311) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 8/249
UVM_ERROR @ 1578965142 ps: (uart_scoreboard.sv:443) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxFrameErr
UVM_ERROR @ 1578965142 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxFrameErr