Simulation Results: ac_range_check

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 83.29 %
  • code
  • 93.53 %
  • assert
  • 97.75 %
  • func
  • 58.58 %
  • block
  • 99.10 %
  • line
  • 99.93 %
  • branch
  • 98.24 %
  • toggle
  • 82.43 %
Validation stages
V1
98.11%
V2
100.00%
V2S
100.00%
V3
90.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_smoke 20 20 100.00
ac_range_check_smoke 59.000s 7521.426us 20 20 100.00
ac_range_check_smoke_racl 19 20 95.00
ac_range_check_smoke_racl 100.000s 2953.166us 19 20 95.00
csr_hw_reset 1 1 100.00
ac_range_check_csr_hw_reset 2.000s 38.063us 1 1 100.00
csr_rw 5 5 100.00
ac_range_check_csr_rw 4.000s 41.576us 5 5 100.00
csr_bit_bash 1 1 100.00
ac_range_check_csr_bit_bash 60.000s 6490.586us 1 1 100.00
csr_aliasing 1 1 100.00
ac_range_check_csr_aliasing 6.000s 277.324us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
ac_range_check_csr_mem_rw_with_rand_reset 4.000s 88.811us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
ac_range_check_csr_rw 4.000s 41.576us 5 5 100.00
ac_range_check_csr_aliasing 6.000s 277.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
ac_range_check_lock_range 20 20 100.00
ac_range_check_lock_range 16.000s 24.589us 20 20 100.00
ac_range_bypass_enable 1 1 100.00
ac_range_check_bypass 39.000s 1947.414us 1 1 100.00
stress_all 10 10 100.00
ac_range_check_stress_all 330.000s 15393.953us 10 10 100.00
alert_test 10 10 100.00
ac_range_check_alert_test 3.000s 46.594us 10 10 100.00
intr_test 10 10 100.00
ac_range_check_intr_test 15.000s 14.462us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
ac_range_check_tl_errors 6.000s 481.333us 25 25 100.00
tl_d_illegal_access 25 25 100.00
ac_range_check_tl_errors 6.000s 481.333us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 38.063us 1 1 100.00
ac_range_check_csr_rw 4.000s 41.576us 5 5 100.00
ac_range_check_csr_aliasing 6.000s 277.324us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 188.351us 5 5 100.00
tl_d_partial_access 12 12 100.00
ac_range_check_csr_hw_reset 2.000s 38.063us 1 1 100.00
ac_range_check_csr_rw 4.000s 41.576us 5 5 100.00
ac_range_check_csr_aliasing 6.000s 277.324us 1 1 100.00
ac_range_check_same_csr_outstanding 7.000s 188.351us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 20 20 100.00
ac_range_check_shadow_reg_errors 32.000s 1878.115us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
ac_range_check_shadow_reg_errors 32.000s 1878.115us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
ac_range_check_shadow_reg_errors 32.000s 1878.115us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
ac_range_check_shadow_reg_errors 32.000s 1878.115us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
ac_range_check_shadow_reg_errors_with_csr_rw 150.000s 5115.627us 20 20 100.00
tl_intg_err 30 30 100.00
ac_range_check_sec_cm 2.000s 14.322us 5 5 100.00
ac_range_check_tl_intg_err 15.000s 1666.276us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 9 10 90.00
ac_range_check_stress_all_with_rand_reset 412.000s 12697.657us 9 10 90.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 20 20 100.00
ac_range_check_smoke_high_threshold 57.000s 4335.954us 20 20 100.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [ac_range_check_common_vseq] wait timeout occurred! 1 test run
ac_range_check_stress_all_with_rand_reset 113451315225995579582922916740381615158937719342030587323152140892991946763562 39028
UVM_INFO @ 12697656962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (ac_range_check_scoreboard.sv:373) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: ac_range_check_reg_block.intr_state 1 test run
ac_range_check_smoke_racl 28257906268086634086827589431242091114228711717113232058484049176339699700780 4050
UVM_INFO @ 2481014758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---