Simulation Results

Simulation Results: clkmgr

18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.58 %

code
70.02 %

assert
90.91 %

func
74.80 %

line
82.37 %

branch
87.53 %

cond
80.22 %

toggle
100.00 %

FSM
0.00 %

Validation stages

V1		73.91%
V2		66.67%
V2S		34.29%
V3		0.00%

17/23 passed

73.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				10	10	100.00
	clkmgr_smoke	2.460s	91.533us	10	10	100.00
csr_hw_reset				1	1	100.00
	clkmgr_csr_hw_reset	3.300s	179.544us	1	1	100.00
csr_rw				1	5	20.00
	clkmgr_csr_rw	1.520s	45.908us	1	5	20.00
csr_bit_bash				0	1	0.00
	clkmgr_csr_bit_bash	4.480s	195.768us	0	1	0.00
csr_aliasing				1	1	100.00
	clkmgr_csr_aliasing	1.630s	41.148us	1	1	100.00
csr_mem_rw_with_rand_reset				4	5	80.00
	clkmgr_csr_mem_rw_with_rand_reset	3.450s	164.778us	4	5	80.00
regwen_csr_and_corresponding_lockable_csr				2	6	33.33
	clkmgr_csr_rw	1.520s	45.908us	1	5	20.00
	clkmgr_csr_aliasing	1.630s	41.148us	1	1	100.00

78/117 passed

66.67 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
peri_enables				10	10	100.00
	clkmgr_peri	2.410s	106.934us	10	10	100.00
trans_enables				10	10	100.00
	clkmgr_trans	2.060s	74.450us	10	10	100.00
clk_status				10	10	100.00
	clkmgr_clk_status	3.170s	185.415us	10	10	100.00
jitter				10	10	100.00
	clkmgr_smoke	2.460s	91.533us	10	10	100.00
frequency				0	10	0.00
	clkmgr_frequency	1.890s	63.361us	0	10	0.00
frequency_timeout				0	10	0.00
	clkmgr_frequency_timeout	1.000s	6.482us	0	10	0.00
frequency_overflow				0	10	0.00
	clkmgr_frequency	1.890s	63.361us	0	10	0.00
stress_all				0	10	0.00
	clkmgr_stress_all	1.600s	93.989us	0	10	0.00
alert_test				10	10	100.00
	clkmgr_alert_test	1.610s	43.981us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	clkmgr_tl_errors	17.760s	1120.531us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	clkmgr_tl_errors	17.760s	1120.531us	25	25	100.00
tl_d_outstanding_access				3	12	25.00
	clkmgr_csr_hw_reset	3.300s	179.544us	1	1	100.00
	clkmgr_csr_rw	1.520s	45.908us	1	5	20.00
	clkmgr_csr_aliasing	1.630s	41.148us	1	1	100.00
	clkmgr_same_csr_outstanding	3.110s	165.782us	0	5	0.00
tl_d_partial_access				3	12	25.00
	clkmgr_csr_hw_reset	3.300s	179.544us	1	1	100.00
	clkmgr_csr_rw	1.520s	45.908us	1	5	20.00
	clkmgr_csr_aliasing	1.630s	41.148us	1	1	100.00
	clkmgr_same_csr_outstanding	3.110s	165.782us	0	5	0.00

V2S

36/105 passed

34.29 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				5	30	16.67
	clkmgr_sec_cm	15.090s	949.826us	5	5	100.00
	clkmgr_tl_intg_err	3.230s	166.996us	0	25	0.00
shadow_reg_update_error				20	20	100.00
	clkmgr_shadow_reg_errors	8.880s	612.369us	20	20	100.00
shadow_reg_read_clear_staged_value				20	20	100.00
	clkmgr_shadow_reg_errors	8.880s	612.369us	20	20	100.00
shadow_reg_storage_error				20	20	100.00
	clkmgr_shadow_reg_errors	8.880s	612.369us	20	20	100.00
shadowed_reset_glitch				20	20	100.00
	clkmgr_shadow_reg_errors	8.880s	612.369us	20	20	100.00
shadow_reg_update_error_with_csr_rw				0	20	0.00
	clkmgr_shadow_reg_errors_with_csr_rw	1.710s	46.950us	0	20	0.00
sec_cm_bus_integrity				0	25	0.00
	clkmgr_tl_intg_err	3.230s	166.996us	0	25	0.00
sec_cm_meas_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency	1.890s	63.361us	0	10	0.00
sec_cm_timeout_clk_bkgn_chk				0	10	0.00
	clkmgr_frequency_timeout	1.000s	6.482us	0	10	0.00
sec_cm_meas_config_shadow				20	20	100.00
	clkmgr_shadow_reg_errors	8.880s	612.369us	20	20	100.00
sec_cm_idle_intersig_mubi				10	10	100.00
	clkmgr_idle_intersig_mubi	3.970s	201.726us	10	10	100.00
sec_cm_jitter_config_mubi				1	5	20.00
	clkmgr_csr_rw	1.520s	45.908us	1	5	20.00
sec_cm_idle_ctr_redun				5	5	100.00
	clkmgr_sec_cm	15.090s	949.826us	5	5	100.00
sec_cm_meas_config_regwen				1	5	20.00
	clkmgr_csr_rw	1.520s	45.908us	1	5	20.00
sec_cm_clk_ctrl_config_regwen				1	5	20.00
	clkmgr_csr_rw	1.520s	45.908us	1	5	20.00
prim_count_check				5	5	100.00
	clkmgr_sec_cm	15.090s	949.826us	5	5	100.00

0/20 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
regwen				10
	clkmgr_regwen	1.290s	22.011us	10
stress_all_with_rand_reset				10
	clkmgr_stress_all_with_rand_reset	103.490s	8444.872us	10

Error Messages

	Test	seed	line	log context
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen.en reset value:				26 test runs
	clkmgr_csr_rw	2290400950994068174602879391019154778425495507235118559927478511783283443220	81	UVM_INFO @ 3946223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	73877032302597435565301971669397793167378096127698891751131178749701129286412	81	UVM_INFO @ 2497732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	10425578770397136180382640527292374108131907689123232046532326798438280375974	81	UVM_INFO @ 9917520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	49058366522963047420955086735070119844475368148905217816795974587277477636622	107	UVM_INFO @ 13106303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	112883227240521851003762602897115185467149697851109127323834750794469182901089	81	UVM_INFO @ 3091488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	66983107924071565876890320352475480248742827848149026402227060023827184318927	81	UVM_INFO @ 1857664 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_mem_rw_with_rand_reset	72912268848126423494874608429587581896875311313071465122030131443794977883398	82	UVM_INFO @ 1659532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	78014837863139902391248757502776070400535472414604501380865681303224230089759	107	UVM_INFO @ 23430346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	469572909339853470892130469809617300738684524073337406996048873042166194012	81	UVM_INFO @ 4593962 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	100518902218482244690861098118964607145641546281811068980953234731195176503581	81	UVM_INFO @ 4988221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	99725785359784985305266258317734528868443912388972696184250213213556963082430	119	UVM_INFO @ 21091079 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	59864327695192287268164050059730442710941726049862684435525541105916378942727	81	UVM_INFO @ 46949569 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	99019269815917261437428271341464495986545951411466110526451552305317602695647	145	UVM_INFO @ 58976708 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	3754955791674485581662922764156914857337712112125554623333711042879664473050	81	UVM_INFO @ 5268157 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	15060604951854409455589745790061279423913785835968616519323888736339221357386	89	UVM_INFO @ 12617247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	35138355053691230482970017062002020665289515658395012794943456975738833356512	81	UVM_INFO @ 1935990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	84269460199811323314741925562610762354243393877214857675495106873244371421058	104	UVM_INFO @ 16894602 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	98554763035486764574042645885977612359063498658177775093252340158171238392223	81	UVM_INFO @ 9605002 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	8938659148862211901760637559358819397301847038109854116341454814604779618203	108	UVM_INFO @ 166995959 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	95205368689786709666327002196842078297655115466561936368031501149925069300618	81	UVM_INFO @ 6539566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	95330499978833165766313141784499269984399614483471511933057878774876360976252	81	UVM_INFO @ 5730902 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	74248614115168652404526057307097272303484232518262972826779636607402051561361	85	UVM_INFO @ 16197889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	24629518862466561154783857327936953645230563675215912395951296137459811231700	99	UVM_INFO @ 24607364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	105186688889629212965344281445490801602072668846055187646155143649318080382171	81	UVM_INFO @ 2062127 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	52935444591539595106838688679323689402651022481275338074596047548538752671035	106	UVM_INFO @ 78885661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	51574919421708362386458867892127441093415228634100733757673383894082027726246	93	UVM_INFO @ 56212899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value:				24 test runs
	clkmgr_shadow_reg_errors_with_csr_rw	86003829428426143023678762231182658357877553455561510229823447041904484916629	81	UVM_INFO @ 9760084 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	77833961178865145806495378208371556072350078311880860574313255805565871854778	95	UVM_INFO @ 25228242 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_csr_rw	25738962452546465270430346757476419745014163313143880266792201747925989413461	81	UVM_INFO @ 13432732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	52319954225330407514195336229804105115562875028650964741086989975689692749039	81	UVM_INFO @ 3323204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	58901636852052651012901253984152110992453210349974717727722613906438348440267	88	UVM_INFO @ 3654670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	72670301388817244576525630564778060464284316353300156039595563138691425450702	81	UVM_INFO @ 3850895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	13308976421887793034905107453228274172034559010882435243549972787136571867865	85	UVM_INFO @ 6613415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	109489792574759519575314222916666821494192539807815245863271435273941419763900	92	UVM_INFO @ 15098031 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	24002187556247061374752997513850886811457385527061349065118399231450756246833	81	UVM_INFO @ 6654222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	5244468865012003546481261701629755423525498799466662627330341639500997337547	84	UVM_INFO @ 4673614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	107974498204694129960705501698533934289253449357018130082132623405962567654635	81	UVM_INFO @ 5745527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	4572243796584923687796337392590227591283791510981307277105066531971774252421	91	UVM_INFO @ 3756525 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	97472776225901765645814855301728929340823308521986007747731063334575477298479	81	UVM_INFO @ 3281052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	40178988623057341467539593668441238276431364040147820391944316982346810734042	81	UVM_INFO @ 3365793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	56131660709758655698017877203707191296087337107592873504164110157965346877812	81	UVM_INFO @ 3337800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	68492250448227382731046210931326086218880143877184822773623411679556401083621	81	UVM_INFO @ 15716492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	49258528937418681651449320460082319017895583380956500648372066712217175721001	81	UVM_INFO @ 11558311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	81083725878564729455289357712021733207580425419609284857539686868286357254915	81	UVM_INFO @ 3462294 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	101182184274863273017177460999790871709524731914230897973131682010375067936351	88	UVM_INFO @ 2880096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	13807438201616288916593314820048252621973949186868239376507514680821185426875	81	UVM_INFO @ 11204301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	50996860709330488826711740827889426662059570430174807146561320370329430836938	88	UVM_INFO @ 6760907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	31441501844882112908731951259842999299120631892599445507806178849526110166946	114	UVM_INFO @ 32331783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_shadow_reg_errors_with_csr_rw	33113500856113260868853602334759222923953473010097538816279109125791359568603	81	UVM_INFO @ 6424727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_tl_intg_err	18489596302727987767600373581002436505416326235282548916899203878061518110798	89	UVM_INFO @ 14525625 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected b, got b				21 test runs
	clkmgr_frequency_timeout	23470096463557378610924626710951744317598869547301604458115984969492256923451	84	UVM_INFO @ 3213955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	101544756226413368952621357327974830090935482872154661745031847721108187817741	83	UVM_INFO @ 4234379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	93027248854764969833227249414907887467126367564728468183682778555942232621688	84	UVM_INFO @ 3793344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	5677010810518779518268187715474186218278164581303080375083479319555327280736	121	UVM_INFO @ 27528737 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	8978552251219536302638042021365602727230068047465682106028043097554117536013	83	UVM_INFO @ 3433151 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	334197537010073447805657717143411151667551599284336845313556904492059540708	108	UVM_INFO @ 20036164 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	85769246339573129255442785384680395008769688844637184265241415298515500146722	84	UVM_INFO @ 4125201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	96207659054636147482259596939713515596790108843899893565490467583677453903018	84	UVM_INFO @ 3542760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	95638484461981123483165581119602592139212374226373750752813822171162452741090	178	UVM_INFO @ 3167691559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	99526883564933676264631613781346893597052707659463859575459946162606666748507	84	UVM_INFO @ 3878791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	25931276055266768539830142891092650316297141757093473773721730420019608927955	84	UVM_INFO @ 2293251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	9848965975196340442416816986669765631916830441780120860674114218175091023579	85	UVM_INFO @ 21953897 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	81890593429863521662540353833648933360634972386673222721162775754990858480514	84	UVM_INFO @ 55895024 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	11944147587205294255093571360424594017984208512426417070964908024525378903102	84	UVM_INFO @ 3145237 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	13732178121895067994783931509364299164229756733482251990652899718193325649872	85	UVM_INFO @ 3715443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	88055959940374795571524232187222931795919573309136415337810890224800055373527	84	UVM_INFO @ 6482388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	33254972594983371002331524820048532312641774636677894734815168801110809814541	85	UVM_INFO @ 18483603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	41887975937292609255718035861123958934734886776105229368659839561509413499682	124	UVM_INFO @ 47310494 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency_timeout	33181015816116056136400904943495086140068360398580553840562750226107252377650	84	UVM_INFO @ 3464317 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	102866040808377602639551347002846304504063251574953462969981085328711839041396	91	UVM_INFO @ 99342646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	102466941478971623851066970533599059732716316899655665927524427735905126325829	84	UVM_INFO @ 93988871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected b, got b				19 test runs
	clkmgr_frequency	76007766906042763348727800697307602325102971839435633881053446477833243333705	81	UVM_INFO @ 7092734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	72531626305246687678243788426030510343229752639603044725753574442333755380456	218	UVM_INFO @ 113342400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	110623012239148404677064074608076768954453181180925723022819631521661375858776	82	UVM_INFO @ 29568685 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	5647653398296549907024774475597658225200893842642880338371803016695517471337	81	UVM_INFO @ 10640200 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	107134839503892183988651239691642310876205194500932373862509356510560180337434	82	UVM_INFO @ 5244671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	17057816051566548197445067732541348926324689940550003641041383918289182009265	262	UVM_INFO @ 8444872389 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	24530157487524377817699084327082381406996999438961622273119504340415460571664	82	UVM_INFO @ 11142391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	14739286154544010914151023903426510000021199515534260496673622477763563115968	103	UVM_INFO @ 17847946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	44776576813599219619266499728642791722837983141181399716327027577570435940697	82	UVM_INFO @ 19344619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	584698168023989980021821319647253250893879078612222107722380729254699040847	84	UVM_INFO @ 16111213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	96647756871738077254073452969516143401222580172726403846901088211835554524160	146	UVM_INFO @ 67193230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	83911730209585119358218867025635829609208404028354524332794566654366394069371	81	UVM_INFO @ 6702724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all_with_rand_reset	93339417433862550636083564654740461008761485155142596980679766762618215122903	84	UVM_INFO @ 250359082 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	14486445480626254144673564899726814283582400799706907431910768841776123927395	82	UVM_INFO @ 4325751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	86883424059594140375228931085409923890793884487862623168311037561526225768776	81	UVM_INFO @ 8715043 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	100535164840001244418764692015867699812383244273401795223554498311218336949495	81	UVM_INFO @ 5409609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_stress_all	54713290081975276976509591565843915618512665689435262880899876928861810681032	82	UVM_INFO @ 59823321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	108108917170196779246609123135758664156708249671492244440383044903399407296241	82	UVM_INFO @ 63360686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_frequency	60833507902218677318366731301043445101148242853271321244516767118062473132934	81	UVM_INFO @ 6159403 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:660) [clkmgr_common_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				5 test runs
	clkmgr_same_csr_outstanding	21665147269941996117885358257353297969047687532237285866416789510211483752577	81	UVM_INFO @ 30213974 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	42278231755896654503891057123952167866587111791590684719874149940020842849043	81	UVM_INFO @ 10113570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	40950719256499402736469387182624828599572044047683277576982120397045466718738	81	UVM_INFO @ 2908351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	74156903568041758057117534169822327442807068675882069783576778251346614091468	81	UVM_INFO @ 33677430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_same_csr_outstanding	68231475646624751079793164440078722609919759107277353107474888771201067766978	81	UVM_INFO @ 165782073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_en				4 test runs
	clkmgr_regwen	87047926952645088334677143142106710707925536485507187717749409760607743219276	80	UVM_INFO @ 3174877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	82025949011326980827479058336688551354514722939827756048053701831420072173160	80	UVM_INFO @ 2860118 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	106494841044901890371732229315704522258505028371439843803481458338111025560419	80	UVM_INFO @ 6406715 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	70564101517837993515455629500056283662104817639703534793481155360122509812538	80	UVM_INFO @ 1845912 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.main_meas_ctrl_en				3 test runs
	clkmgr_regwen	49207772856491661149291744919958453455581954711528960755036512592008956190897	80	UVM_INFO @ 22011381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	109484302814832634360821260510509778572643064369586900389728584721108091356913	80	UVM_INFO @ 14387783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	5236841085295684898353958887718114907862589563086231248638055151258842875804	80	UVM_INFO @ 3650588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_scoreboard.sv:254) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*]) reg name: clkmgr_reg_block.io_meas_ctrl_shadowed				3 test runs
	clkmgr_regwen	4640697432634038887242494714566061861175885486574913621716543870200402924939	80	UVM_INFO @ 5966401 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	1393372743383622220890767737392618118530533347249849581053484043910060828937	80	UVM_INFO @ 3711041 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	clkmgr_regwen	5114206081495572122179356827608875459975558991737137721913374841883798999378	80	UVM_INFO @ 10079507 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:461) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_] Check failed obs == exp ( [] vs []) Regname: clkmgr_reg_block.measure_ctrl_regwen reset value: Wrote clkmgr_reg_block.measure_ctrl_regwen[]:				1 test run
	clkmgr_csr_bit_bash	107508492234219391101059450316201785189347436406826203711426837495036764551076	81	UVM_INFO @ 195767810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---