Simulation Results: csrng

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.18 %
  • code
  • 96.19 %
  • assert
  • 97.16 %
  • func
  • 92.20 %
  • block
  • 98.50 %
  • line
  • 99.54 %
  • branch
  • 96.32 %
  • toggle
  • 93.64 %
  • FSM
  • 95.24 %
Validation stages
V1
100.00%
V2
99.85%
V2S
99.69%
V3
10.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 25 25 100.00
csrng_smoke 4.000s 74.917us 25 25 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 25.061us 1 1 100.00
csr_rw 5 5 100.00
csrng_csr_rw 3.000s 53.338us 5 5 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 19.000s 767.280us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 13.645us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
csrng_csr_mem_rw_with_rand_reset 5.000s 58.336us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
csrng_csr_rw 3.000s 53.338us 5 5 100.00
csrng_csr_aliasing 2.000s 13.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 200 200 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
alerts 500 500 100.00
csrng_alert 69.000s 4441.487us 500 500 100.00
err 500 500 100.00
csrng_err 9.000s 27.052us 500 500 100.00
cmds 25 25 100.00
csrng_cmds 481.000s 23119.894us 25 25 100.00
life cycle 25 25 100.00
csrng_cmds 481.000s 23119.894us 25 25 100.00
stress_all 23 25 92.00
csrng_stress_all 1649.000s 60329.590us 23 25 92.00
intr_test 10 10 100.00
csrng_intr_test 3.000s 12.953us 10 10 100.00
alert_test 10 10 100.00
csrng_alert_test 3.000s 31.197us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
csrng_tl_errors 21.000s 1277.260us 25 25 100.00
tl_d_illegal_access 25 25 100.00
csrng_tl_errors 21.000s 1277.260us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
csrng_csr_hw_reset 2.000s 25.061us 1 1 100.00
csrng_csr_rw 3.000s 53.338us 5 5 100.00
csrng_csr_aliasing 2.000s 13.645us 1 1 100.00
csrng_same_csr_outstanding 5.000s 94.756us 5 5 100.00
tl_d_partial_access 12 12 100.00
csrng_csr_hw_reset 2.000s 25.061us 1 1 100.00
csrng_csr_rw 3.000s 53.338us 5 5 100.00
csrng_csr_aliasing 2.000s 13.645us 1 1 100.00
csrng_same_csr_outstanding 5.000s 94.756us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 28 30 93.33
csrng_sec_cm 7.000s 333.206us 5 5 100.00
csrng_tl_intg_err 355.000s 10062.892us 23 25 92.00
sec_cm_config_regwen 30 30 100.00
csrng_regwen 8.000s 69.863us 25 25 100.00
csrng_csr_rw 3.000s 53.338us 5 5 100.00
sec_cm_config_mubi 500 500 100.00
csrng_alert 69.000s 4441.487us 500 500 100.00
sec_cm_intersig_mubi 23 25 92.00
csrng_stress_all 1649.000s 60329.590us 23 25 92.00
sec_cm_main_sm_fsm_sparse 705 705 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
csrng_sec_cm 7.000s 333.206us 5 5 100.00
sec_cm_cmd_stage_fsm_sparse 705 705 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
csrng_sec_cm 7.000s 333.206us 5 5 100.00
sec_cm_ctr_drbg_fsm_sparse 705 705 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
csrng_sec_cm 7.000s 333.206us 5 5 100.00
sec_cm_ctr_drbg_ctr_redun 705 705 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
csrng_sec_cm 7.000s 333.206us 5 5 100.00
sec_cm_gen_cmd_ctr_redun 705 705 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
csrng_sec_cm 7.000s 333.206us 5 5 100.00
sec_cm_ctrl_mubi 500 500 100.00
csrng_alert 69.000s 4441.487us 500 500 100.00
sec_cm_main_sm_ctr_local_esc 700 700 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
sec_cm_constants_lc_gated 23 25 92.00
csrng_stress_all 1649.000s 60329.590us 23 25 92.00
sec_cm_sw_genbits_bus_consistency 500 500 100.00
csrng_alert 69.000s 4441.487us 500 500 100.00
sec_cm_tile_link_bus_integrity 23 25 92.00
csrng_tl_intg_err 355.000s 10062.892us 23 25 92.00
sec_cm_aes_cipher_fsm_sparse 705 705 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
csrng_sec_cm 7.000s 333.206us 5 5 100.00
sec_cm_aes_cipher_fsm_redun 700 700 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
sec_cm_aes_cipher_ctrl_sparse 700 700 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
sec_cm_aes_cipher_fsm_local_esc 700 700 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
sec_cm_aes_cipher_ctr_redun 705 705 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
csrng_sec_cm 7.000s 333.206us 5 5 100.00
sec_cm_aes_cipher_data_reg_local_esc 700 700 100.00
csrng_intr 28.000s 1799.473us 200 200 100.00
csrng_err 9.000s 27.052us 500 500 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 10 10.00
csrng_stress_all_with_rand_reset 603.000s 40093.719us 1 10 10.00

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:1230) [csrng_common_vseq] Check failed (vseq_done) 7 test runs
csrng_stress_all_with_rand_reset 47574386264820351935169838742120054291493719610178513150565272214196315826238 133
UVM_INFO @ 1165423455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 91946405055978645337438582861084061298801857189706589828270887261194134591082 219
UVM_INFO @ 1002907206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 4756281748221178821989186136431788997355051108404344191839556989371471419409 145
UVM_INFO @ 745532905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 101861120056299175891109772664649095650330228083529951974903248483694495447571 122
UVM_INFO @ 8241910 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 47361146211323565015935123829100684561505037311495107981029626124409178907897 108
UVM_INFO @ 15807857 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 101954041760575484684916780725072598390563255435165238482490482923604117733510 112
UVM_INFO @ 21747828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 98802022830911693663821459481869877044538391222837034394624104463556759323868 143
UVM_INFO @ 12512818575 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:180) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 3 test runs
csrng_stress_all 10912161909960217110991527998642402749444706206593874399040779639426687996571 125
UVM_INFO @ 14559458193 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all_with_rand_reset 36981264505002637523032134691720141902858681095024936833956774215875184439051 118
UVM_INFO @ 168375899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_stress_all 82643005366897621884670396111415628731546330910709168314079504521722478136549 118
UVM_INFO @ 19041178247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [csrng_common_vseq] wait timeout occurred! 2 test runs
csrng_stress_all_with_rand_reset 113561259235362820932283299140375307049350162704166977799555329057098095955346 184
UVM_INFO @ 13080230099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
csrng_tl_intg_err 66914028685591228928293228992291108630450806954203319329008198778552874980245 114
UVM_INFO @ 10062891856 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [csrng_common_vseq] Expected alert (fatal_alert) did not fire in * cycles. 1 test run
csrng_tl_intg_err 107849146784121116343933363711154452189301908300297238821471094068589519577041 237
UVM_INFO @ 358332670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---