Simulation Results: dma

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.78 %
  • code
  • 90.76 %
  • assert
  • 96.61 %
  • func
  • 75.96 %
  • block
  • 97.38 %
  • line
  • 96.89 %
  • branch
  • 95.83 %
  • toggle
  • 77.37 %
  • FSM
  • 92.96 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
96.77%
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_smoke 25 25 100.00
dma_memory_smoke 16.000s 1263.500us 25 25 100.00
dma_handshake_smoke 25 25 100.00
dma_handshake_smoke 10.000s 2047.256us 25 25 100.00
dma_generic_smoke 50 50 100.00
dma_generic_smoke 12.000s 4529.898us 50 50 100.00
csr_hw_reset 1 1 100.00
dma_csr_hw_reset 2.000s 58.225us 1 1 100.00
csr_rw 5 5 100.00
dma_csr_rw 2.000s 95.688us 5 5 100.00
csr_bit_bash 1 1 100.00
dma_csr_bit_bash 11.000s 4017.408us 1 1 100.00
csr_aliasing 1 1 100.00
dma_csr_aliasing 3.000s 526.666us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
dma_csr_mem_rw_with_rand_reset 2.000s 29.185us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
dma_csr_rw 2.000s 95.688us 5 5 100.00
dma_csr_aliasing 3.000s 526.666us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_memory_region_lock 5 5 100.00
dma_memory_region_lock 185.000s 27485.029us 5 5 100.00
dma_memory_tl_error 3 3 100.00
dma_memory_stress 1198.000s 91396.175us 3 3 100.00
dma_handshake_tl_error 3 3 100.00
dma_handshake_stress 579.000s 75331.923us 3 3 100.00
dma_handshake_stress 3 3 100.00
dma_handshake_stress 579.000s 75331.923us 3 3 100.00
dma_memory_stress 3 3 100.00
dma_memory_stress 1198.000s 91396.175us 3 3 100.00
dma_generic_stress 5 5 100.00
dma_generic_stress 2125.000s 499376.368us 5 5 100.00
dma_handshake_mem_buffer_overflow 3 3 100.00
dma_handshake_stress 579.000s 75331.923us 3 3 100.00
dma_abort 5 5 100.00
dma_abort 21.000s 1102.247us 5 5 100.00
dma_stress_all 3 3 100.00
dma_stress_all 307.000s 62493.316us 3 3 100.00
alert_test 10 10 100.00
dma_alert_test 2.000s 18.250us 10 10 100.00
intr_test 10 10 100.00
dma_intr_test 2.000s 45.406us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
dma_tl_errors 9.000s 31.563us 25 25 100.00
tl_d_illegal_access 25 25 100.00
dma_tl_errors 9.000s 31.563us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
dma_csr_hw_reset 2.000s 58.225us 1 1 100.00
dma_csr_rw 2.000s 95.688us 5 5 100.00
dma_csr_aliasing 3.000s 526.666us 1 1 100.00
dma_same_csr_outstanding 4.000s 522.649us 5 5 100.00
tl_d_partial_access 12 12 100.00
dma_csr_hw_reset 2.000s 58.225us 1 1 100.00
dma_csr_rw 2.000s 95.688us 5 5 100.00
dma_csr_aliasing 3.000s 526.666us 1 1 100.00
dma_same_csr_outstanding 4.000s 522.649us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dma_illegal_addr_range 13 13 100.00
dma_mem_enabled 34.000s 1895.519us 5 5 100.00
dma_generic_stress 2125.000s 499376.368us 5 5 100.00
dma_handshake_stress 579.000s 75331.923us 3 3 100.00
dma_config_lock 15 15 100.00
dma_config_lock 13.000s 321.049us 15 15 100.00
tl_intg_err 30 30 100.00
dma_tl_intg_err 8.000s 100.884us 25 25 100.00
dma_sec_cm 1.000s 19.529us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 30 31 96.77
dma_short_transfer 244.000s 19765.090us 25 25 100.00
dma_longer_transfer 18.000s 2510.380us 5 5 100.00
dma_stress_all_with_rand_reset 13.000s 1201.950us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR @ *ps: (cip_base_vseq.sv:1297) [dma_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
dma_stress_all_with_rand_reset 33059949162258863487118852706675581107574026720284417859137941402906342288601 108
UVM_INFO @ 1201950294ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---