Simulation Results: edn/edn0

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 84.27 %
  • code
  • 95.31 %
  • assert
  • 98.89 %
  • func
  • 58.60 %
  • block
  • 96.99 %
  • line
  • 98.68 %
  • branch
  • 93.33 %
  • toggle
  • 89.22 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
96.67%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 2.000s 33.427us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 2.000s 46.512us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 2.000s 53.170us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 8.000s 328.341us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 3.000s 103.782us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.000s 342.602us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 2.000s 53.170us 5 5 100.00
edn_csr_aliasing 3.000s 103.782us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.000s 203.680us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.000s 203.680us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.000s 203.680us 100 100 100.00
interrupts 20 20 100.00
edn_intr 2.000s 57.481us 20 20 100.00
alerts 200 200 100.00
edn_alert 7.000s 25.542us 200 200 100.00
errs 100 100 100.00
edn_err 3.000s 74.492us 100 100 100.00
disable 100 100 100.00
edn_disable 2.000s 32.916us 50 50 100.00
edn_disable_auto_req_mode 3.000s 97.132us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 9.000s 534.432us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 2.000s 18.577us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 4.000s 47.320us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 6.000s 1713.737us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 6.000s 1713.737us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 2.000s 46.512us 1 1 100.00
edn_csr_rw 2.000s 53.170us 5 5 100.00
edn_csr_aliasing 3.000s 103.782us 1 1 100.00
edn_same_csr_outstanding 3.000s 35.959us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 2.000s 46.512us 1 1 100.00
edn_csr_rw 2.000s 53.170us 5 5 100.00
edn_csr_aliasing 3.000s 103.782us 1 1 100.00
edn_same_csr_outstanding 3.000s 35.959us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 13.000s 1138.861us 5 5 100.00
edn_tl_intg_err 4.000s 133.588us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 2.000s 23.147us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 7.000s 25.542us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 13.000s 1138.861us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 13.000s 1138.861us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 13.000s 1138.861us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 13.000s 1138.861us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 7.000s 25.542us 200 200 100.00
edn_sec_cm 13.000s 1138.861us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 7.000s 25.542us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 4.000s 133.588us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 29 30 96.67
edn_stress_all_with_rand_reset 205.000s 11639.620us 29 30 96.67

Error Messages

   Test seed line log context
UVM_FATAL (cip_base_vseq.sv:465) [edn_common_vseq] wait timeout occurred! 1 test run
edn_stress_all_with_rand_reset 12217721195205435321969550454720648531055088554285276609573310891180839315107 205
UVM_INFO @ 11639619989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---