Simulation Results: edn/edn1

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.65 %
  • code
  • 96.39 %
  • assert
  • 97.92 %
  • func
  • 92.65 %
  • line
  • 98.48 %
  • branch
  • 94.59 %
  • cond
  • 95.00 %
  • toggle
  • 96.15 %
  • FSM
  • 97.73 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
edn_smoke 1.300s 18.712us 10 10 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.220s 17.585us 1 1 100.00
csr_rw 5 5 100.00
edn_csr_rw 1.200s 53.319us 5 5 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.010s 214.014us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.190s 64.046us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
edn_csr_mem_rw_with_rand_reset 2.470s 391.939us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
edn_csr_rw 1.200s 53.319us 5 5 100.00
edn_csr_aliasing 1.190s 64.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 100 100 100.00
edn_genbits 5.650s 440.793us 100 100 100.00
csrng_commands 100 100 100.00
edn_genbits 5.650s 440.793us 100 100 100.00
genbits 100 100 100.00
edn_genbits 5.650s 440.793us 100 100 100.00
interrupts 20 20 100.00
edn_intr 1.430s 28.721us 20 20 100.00
alerts 200 200 100.00
edn_alert 1.720s 222.811us 200 200 100.00
errs 100 100 100.00
edn_err 2.070s 37.693us 100 100 100.00
disable 100 100 100.00
edn_disable 1.290s 14.395us 50 50 100.00
edn_disable_auto_req_mode 1.770s 61.199us 50 50 100.00
stress_all 30 30 100.00
edn_stress_all 6.870s 359.561us 30 30 100.00
intr_test 10 10 100.00
edn_intr_test 1.230s 18.407us 10 10 100.00
alert_test 10 10 100.00
edn_alert_test 1.400s 30.420us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
edn_tl_errors 5.770s 1954.695us 25 25 100.00
tl_d_illegal_access 25 25 100.00
edn_tl_errors 5.770s 1954.695us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
edn_csr_hw_reset 1.220s 17.585us 1 1 100.00
edn_csr_rw 1.200s 53.319us 5 5 100.00
edn_csr_aliasing 1.190s 64.046us 1 1 100.00
edn_same_csr_outstanding 1.640s 59.511us 5 5 100.00
tl_d_partial_access 12 12 100.00
edn_csr_hw_reset 1.220s 17.585us 1 1 100.00
edn_csr_rw 1.200s 53.319us 5 5 100.00
edn_csr_aliasing 1.190s 64.046us 1 1 100.00
edn_same_csr_outstanding 1.640s 59.511us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
edn_sec_cm 4.950s 1024.287us 5 5 100.00
edn_tl_intg_err 9.740s 666.051us 25 25 100.00
sec_cm_config_regwen 5 5 100.00
edn_regwen 1.270s 21.133us 5 5 100.00
sec_cm_config_mubi 200 200 100.00
edn_alert 1.720s 222.811us 200 200 100.00
sec_cm_main_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.950s 1024.287us 5 5 100.00
sec_cm_ack_sm_fsm_sparse 5 5 100.00
edn_sec_cm 4.950s 1024.287us 5 5 100.00
sec_cm_fifo_ctr_redun 5 5 100.00
edn_sec_cm 4.950s 1024.287us 5 5 100.00
sec_cm_ctr_redun 5 5 100.00
edn_sec_cm 4.950s 1024.287us 5 5 100.00
sec_cm_main_sm_ctr_local_esc 205 205 100.00
edn_alert 1.720s 222.811us 200 200 100.00
edn_sec_cm 4.950s 1024.287us 5 5 100.00
sec_cm_cs_rdata_bus_consistency 200 200 100.00
edn_alert 1.720s 222.811us 200 200 100.00
sec_cm_tile_link_bus_integrity 25 25 100.00
edn_tl_intg_err 9.740s 666.051us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 30 30 100.00
edn_stress_all_with_rand_reset 128.740s 26809.164us 30 30 100.00