Simulation Results: hmac

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.51 %
  • code
  • 83.35 %
  • assert
  • 97.17 %
  • func
  • 100.00 %
  • block
  • 97.69 %
  • line
  • 98.44 %
  • branch
  • 94.23 %
  • toggle
  • 45.89 %
  • FSM
  • 94.83 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 10 10 100.00
hmac_smoke 20.000s 4935.763us 10 10 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 2.000s 15.085us 1 1 100.00
csr_rw 5 5 100.00
hmac_csr_rw 3.000s 38.258us 5 5 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 22.000s 1705.216us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.000s 126.955us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
hmac_csr_mem_rw_with_rand_reset 1185.000s 401304.415us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
hmac_csr_rw 3.000s 38.258us 5 5 100.00
hmac_csr_aliasing 2.000s 126.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 10 10 100.00
hmac_long_msg 155.000s 12157.862us 10 10 100.00
back_pressure 25 25 100.00
hmac_back_pressure 135.000s 2520.518us 25 25 100.00
test_vectors 365 365 100.00
hmac_test_sha256_vectors 445.000s 41553.621us 30 30 100.00
hmac_test_sha384_vectors 834.000s 18320.510us 75 75 100.00
hmac_test_sha512_vectors 823.000s 45643.167us 75 75 100.00
hmac_test_hmac256_vectors 24.000s 1789.462us 50 50 100.00
hmac_test_hmac384_vectors 26.000s 1208.361us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 703.746us 75 75 100.00
burst_wr 50 50 100.00
hmac_burst_wr 64.000s 6064.458us 50 50 100.00
datapath_stress 10 10 100.00
hmac_datapath_stress 531.000s 11786.437us 10 10 100.00
error 10 10 100.00
hmac_error 175.000s 11559.430us 10 10 100.00
wipe_secret 10 10 100.00
hmac_wipe_secret 183.000s 47284.546us 10 10 100.00
save_and_restore 155 155 100.00
hmac_smoke 20.000s 4935.763us 10 10 100.00
hmac_long_msg 155.000s 12157.862us 10 10 100.00
hmac_back_pressure 135.000s 2520.518us 25 25 100.00
hmac_datapath_stress 531.000s 11786.437us 10 10 100.00
hmac_burst_wr 64.000s 6064.458us 50 50 100.00
hmac_stress_all 1540.000s 915999.728us 50 50 100.00
fifo_empty_status_interrupt 430 430 100.00
hmac_smoke 20.000s 4935.763us 10 10 100.00
hmac_long_msg 155.000s 12157.862us 10 10 100.00
hmac_back_pressure 135.000s 2520.518us 25 25 100.00
hmac_datapath_stress 531.000s 11786.437us 10 10 100.00
hmac_wipe_secret 183.000s 47284.546us 10 10 100.00
hmac_test_sha256_vectors 445.000s 41553.621us 30 30 100.00
hmac_test_sha384_vectors 834.000s 18320.510us 75 75 100.00
hmac_test_sha512_vectors 823.000s 45643.167us 75 75 100.00
hmac_test_hmac256_vectors 24.000s 1789.462us 50 50 100.00
hmac_test_hmac384_vectors 26.000s 1208.361us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 703.746us 75 75 100.00
wide_digest_configurable_key_length 540 540 100.00
hmac_smoke 20.000s 4935.763us 10 10 100.00
hmac_long_msg 155.000s 12157.862us 10 10 100.00
hmac_back_pressure 135.000s 2520.518us 25 25 100.00
hmac_datapath_stress 531.000s 11786.437us 10 10 100.00
hmac_burst_wr 64.000s 6064.458us 50 50 100.00
hmac_error 175.000s 11559.430us 10 10 100.00
hmac_wipe_secret 183.000s 47284.546us 10 10 100.00
hmac_test_sha256_vectors 445.000s 41553.621us 30 30 100.00
hmac_test_sha384_vectors 834.000s 18320.510us 75 75 100.00
hmac_test_sha512_vectors 823.000s 45643.167us 75 75 100.00
hmac_test_hmac256_vectors 24.000s 1789.462us 50 50 100.00
hmac_test_hmac384_vectors 26.000s 1208.361us 60 60 100.00
hmac_test_hmac512_vectors 30.000s 703.746us 75 75 100.00
hmac_stress_all 1540.000s 915999.728us 50 50 100.00
stress_all 50 50 100.00
hmac_stress_all 1540.000s 915999.728us 50 50 100.00
alert_test 10 10 100.00
hmac_alert_test 2.000s 11.367us 10 10 100.00
intr_test 10 10 100.00
hmac_intr_test 2.000s 34.009us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
hmac_tl_errors 6.000s 160.514us 25 25 100.00
tl_d_illegal_access 25 25 100.00
hmac_tl_errors 6.000s 160.514us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
hmac_csr_hw_reset 2.000s 15.085us 1 1 100.00
hmac_csr_rw 3.000s 38.258us 5 5 100.00
hmac_csr_aliasing 2.000s 126.955us 1 1 100.00
hmac_same_csr_outstanding 3.000s 168.713us 5 5 100.00
tl_d_partial_access 12 12 100.00
hmac_csr_hw_reset 2.000s 15.085us 1 1 100.00
hmac_csr_rw 3.000s 38.258us 5 5 100.00
hmac_csr_aliasing 2.000s 126.955us 1 1 100.00
hmac_same_csr_outstanding 3.000s 168.713us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
hmac_sec_cm 2.000s 38.727us 5 5 100.00
hmac_tl_intg_err 7.000s 257.354us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
hmac_tl_intg_err 7.000s 257.354us 25 25 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 10 10 100.00
hmac_smoke 20.000s 4935.763us 10 10 100.00
stress_reset 25 25 100.00
hmac_stress_reset 7.000s 416.488us 25 25 100.00
stress_all_with_rand_reset 35 35 100.00
hmac_stress_all_with_rand_reset 406.000s 7466.811us 35 35 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.000s 18.201us 1 1 100.00