Simulation Results: keymgr_dpe/darjeeling

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 65.87 %
  • code
  • 82.53 %
  • assert
  • 97.21 %
  • func
  • 17.88 %
  • block
  • 98.00 %
  • line
  • 98.70 %
  • branch
  • 93.49 %
  • toggle
  • 56.39 %
  • FSM
  • 81.54 %
Validation stages
V1
95.65%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 9 10 90.00
keymgr_dpe_smoke 18.000s 2670.041us 9 10 90.00
csr_hw_reset 1 1 100.00
keymgr_dpe_csr_hw_reset 1.000s 19.230us 1 1 100.00
csr_rw 5 5 100.00
keymgr_dpe_csr_rw 3.000s 51.938us 5 5 100.00
csr_bit_bash 1 1 100.00
keymgr_dpe_csr_bit_bash 7.000s 506.345us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_dpe_csr_aliasing 2.000s 56.714us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
keymgr_dpe_csr_mem_rw_with_rand_reset 3.000s 42.878us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
keymgr_dpe_csr_rw 3.000s 51.938us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 56.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
intr_test 10 10 100.00
keymgr_dpe_intr_test 2.000s 43.181us 10 10 100.00
alert_test 10 10 100.00
keymgr_dpe_alert_test 3.000s 61.599us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
keymgr_dpe_tl_errors 5.000s 566.765us 25 25 100.00
tl_d_illegal_access 25 25 100.00
keymgr_dpe_tl_errors 5.000s 566.765us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
keymgr_dpe_csr_hw_reset 1.000s 19.230us 1 1 100.00
keymgr_dpe_csr_rw 3.000s 51.938us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 56.714us 1 1 100.00
keymgr_dpe_same_csr_outstanding 4.000s 287.158us 5 5 100.00
tl_d_partial_access 12 12 100.00
keymgr_dpe_csr_hw_reset 1.000s 19.230us 1 1 100.00
keymgr_dpe_csr_rw 3.000s 51.938us 5 5 100.00
keymgr_dpe_csr_aliasing 2.000s 56.714us 1 1 100.00
keymgr_dpe_same_csr_outstanding 4.000s 287.158us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
keymgr_dpe_sec_cm 10.000s 2685.201us 5 5 100.00
keymgr_dpe_tl_intg_err 6.000s 780.461us 25 25 100.00
shadow_reg_update_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 146.029us 20 20 100.00
shadow_reg_read_clear_staged_value 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 146.029us 20 20 100.00
shadow_reg_storage_error 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 146.029us 20 20 100.00
shadowed_reset_glitch 20 20 100.00
keymgr_dpe_shadow_reg_errors 4.000s 146.029us 20 20 100.00
shadow_reg_update_error_with_csr_rw 20 20 100.00
keymgr_dpe_shadow_reg_errors_with_csr_rw 7.000s 494.143us 20 20 100.00
prim_count_check 5 5 100.00
keymgr_dpe_sec_cm 10.000s 2685.201us 5 5 100.00
prim_fsm_check 5 5 100.00
keymgr_dpe_sec_cm 10.000s 2685.201us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert recov_operation_err has unexpected timeout error 1 test run
keymgr_dpe_smoke 59649008804799793821373801335837217704189908116069050366551791410159634634969 2953
UVM_INFO @ 2247314534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---