Simulation Results

Simulation Results: lc_ctrl/volatile_unlock_disabled

18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]

Coverage statistics

Total
92.54 %

code
93.20 %

assert
96.69 %

func
87.74 %

block
96.70 %

line
97.39 %

branch
91.61 %

toggle
88.57 %

FSM
95.24 %

Validation stages

V1		100.00%
V2		92.97%
V2S		98.00%
V3		10.00%

33/33 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				20	20	100.00
	lc_ctrl_smoke	3.000s	88.731us	20	20	100.00
csr_hw_reset				1	1	100.00
	lc_ctrl_csr_hw_reset	22.000s	33.295us	1	1	100.00
csr_rw				5	5	100.00
	lc_ctrl_csr_rw	10.000s	29.696us	5	5	100.00
csr_bit_bash				1	1	100.00
	lc_ctrl_csr_bit_bash	25.000s	439.421us	1	1	100.00
csr_aliasing				1	1	100.00
	lc_ctrl_csr_aliasing	27.000s	324.572us	1	1	100.00
csr_mem_rw_with_rand_reset				5	5	100.00
	lc_ctrl_csr_mem_rw_with_rand_reset	20.000s	29.471us	5	5	100.00
regwen_csr_and_corresponding_lockable_csr				6	6	100.00
	lc_ctrl_csr_rw	10.000s	29.696us	5	5	100.00
	lc_ctrl_csr_aliasing	27.000s	324.572us	1	1	100.00

397/427 passed

92.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
state_post_trans				20	20	100.00
	lc_ctrl_state_post_trans	3.000s	102.423us	20	20	100.00
regwen_during_op				10	10	100.00
	lc_ctrl_regwen_during_op	9.000s	1383.682us	10	10	100.00
rand_wr_claim_transition_if				10	10	100.00
	lc_ctrl_claim_transition_if	28.000s	84.778us	10	10	100.00
lc_prog_failure				20	20	100.00
	lc_ctrl_prog_failure	3.000s	67.640us	20	20	100.00
lc_state_failure				20	20	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
lc_errors				20	20	100.00
	lc_ctrl_errors	12.000s	2216.920us	20	20	100.00
security_escalation				117	140	83.57
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_prog_failure	3.000s	67.640us	20	20	100.00
	lc_ctrl_errors	12.000s	2216.920us	20	20	100.00
	lc_ctrl_security_escalation	6.000s	3557.053us	20	20	100.00
	lc_ctrl_jtag_state_failure	30.000s	2391.457us	4	20	20.00
	lc_ctrl_jtag_prog_failure	7.000s	715.762us	16	20	80.00
	lc_ctrl_jtag_errors	39.000s	33996.169us	17	20	85.00
jtag_access				200	210	95.24
	lc_ctrl_jtag_smoke	6.000s	865.285us	20	20	100.00
	lc_ctrl_jtag_state_post_trans	10.000s	2342.922us	17	20	85.00
	lc_ctrl_jtag_prog_failure	7.000s	715.762us	16	20	80.00
	lc_ctrl_jtag_errors	39.000s	33996.169us	17	20	85.00
	lc_ctrl_jtag_access	11.000s	5179.456us	50	50	100.00
	lc_ctrl_jtag_regwen_during_op	13.000s	1806.890us	10	10	100.00
	lc_ctrl_jtag_csr_hw_reset	4.000s	265.746us	10	10	100.00
	lc_ctrl_jtag_csr_rw	3.000s	674.300us	10	10	100.00
	lc_ctrl_jtag_csr_bit_bash	12.000s	2248.023us	10	10	100.00
	lc_ctrl_jtag_csr_aliasing	3.000s	476.526us	10	10	100.00
	lc_ctrl_jtag_same_csr_outstanding	2.000s	45.081us	10	10	100.00
	lc_ctrl_jtag_csr_mem_rw_with_rand_reset	4.000s	232.328us	10	10	100.00
	lc_ctrl_jtag_alert_test	3.000s	828.159us	10	10	100.00
jtag_priority				10	10	100.00
	lc_ctrl_jtag_priority	49.000s	8220.693us	10	10	100.00
lc_ctrl_volatile_unlock				10	10	100.00
	lc_ctrl_volatile_unlock_smoke	2.000s	13.645us	10	10	100.00
stress_all				6	10	60.00
	lc_ctrl_stress_all	79.000s	29663.995us	6	10	60.00
alert_test				10	10	100.00
	lc_ctrl_alert_test	28.000s	74.500us	10	10	100.00
tl_d_oob_addr_access				25	25	100.00
	lc_ctrl_tl_errors	4.000s	1558.050us	25	25	100.00
tl_d_illegal_access				25	25	100.00
	lc_ctrl_tl_errors	4.000s	1558.050us	25	25	100.00
tl_d_outstanding_access				12	12	100.00
	lc_ctrl_csr_hw_reset	22.000s	33.295us	1	1	100.00
	lc_ctrl_csr_rw	10.000s	29.696us	5	5	100.00
	lc_ctrl_csr_aliasing	27.000s	324.572us	1	1	100.00
	lc_ctrl_same_csr_outstanding	2.000s	104.907us	5	5	100.00
tl_d_partial_access				12	12	100.00
	lc_ctrl_csr_hw_reset	22.000s	33.295us	1	1	100.00
	lc_ctrl_csr_rw	10.000s	29.696us	5	5	100.00
	lc_ctrl_csr_aliasing	27.000s	324.572us	1	1	100.00
	lc_ctrl_same_csr_outstanding	2.000s	104.907us	5	5	100.00

V2S

147/150 passed

98.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				30	30	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
	lc_ctrl_tl_intg_err	3.000s	125.173us	25	25	100.00
sec_cm_bus_integrity				25	25	100.00
	lc_ctrl_tl_intg_err	3.000s	125.173us	25	25	100.00
sec_cm_transition_config_regwen				10	10	100.00
	lc_ctrl_regwen_during_op	9.000s	1383.682us	10	10	100.00
sec_cm_manuf_state_sparse				25	25	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
sec_cm_transition_ctr_sparse				25	25	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
sec_cm_manuf_state_bkgn_chk				25	25	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
sec_cm_transition_ctr_bkgn_chk				25	25	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
sec_cm_state_config_sparse				25	25	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
sec_cm_main_fsm_sparse				25	25	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
sec_cm_kmac_fsm_sparse				25	25	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
sec_cm_main_fsm_local_esc				25	25	100.00
	lc_ctrl_state_failure	7.000s	1372.704us	20	20	100.00
	lc_ctrl_sec_cm	4.000s	249.988us	5	5	100.00
sec_cm_main_fsm_global_esc				20	20	100.00
	lc_ctrl_security_escalation	6.000s	3557.053us	20	20	100.00
sec_cm_main_ctrl_flow_consistency				37	40	92.50
	lc_ctrl_state_post_trans	3.000s	102.423us	20	20	100.00
	lc_ctrl_jtag_state_post_trans	10.000s	2342.922us	17	20	85.00
sec_cm_intersig_mubi				10	10	100.00
	lc_ctrl_sec_mubi	8.000s	1299.167us	10	10	100.00
sec_cm_token_valid_ctrl_mubi				10	10	100.00
	lc_ctrl_sec_mubi	8.000s	1299.167us	10	10	100.00
sec_cm_token_digest				10	10	100.00
	lc_ctrl_sec_token_digest	7.000s	809.056us	10	10	100.00
sec_cm_token_mux_ctrl_redun				10	10	100.00
	lc_ctrl_sec_token_mux	6.000s	1378.019us	10	10	100.00
sec_cm_token_valid_mux_redun				10	10	100.00
	lc_ctrl_sec_token_mux	6.000s	1378.019us	10	10	100.00

1/10 passed

10.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	10	10.00
	lc_ctrl_stress_all_with_rand_reset	53.000s	21656.074us	1	10	10.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error				23 test runs
	lc_ctrl_jtag_state_post_trans	14894522891376055868264119796291273106628205028731358598851829698396372661630	179	UVM_INFO @ 663092181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	52263838759449513205485639588120685961135202988936892884367098199424198384089	178	UVM_INFO @ 128170964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	6943447517463450505793285361916597667942681714361258579630992546158608517711	302	UVM_INFO @ 1358249496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	24032628376083044667373261681739835065785129089636628450715650461127438838914	445	UVM_INFO @ 1833810624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	7644235488152780777525913001794333074541493883657647861133332320265787340730	1238	UVM_INFO @ 1842124875 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	72556645270079245275086648238836056837551624489743533139878602592620085675881	930	UVM_INFO @ 3029306245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	8217754886180046806933158829874565214186552410914316236512332493233139708029	719	UVM_INFO @ 468314674 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	56839043415995689219704757248875515190795361600947077853911657880662170534832	683	UVM_INFO @ 464030385 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	61594960808065200587736243745324815010389330916231937745903499119373141665226	259	UVM_INFO @ 578330475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	59878598079658851797309127320787592222127485225247892484106791870118252669899	217	UVM_INFO @ 454248360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	41259016902836261291162083649076384500948200674345909137209753365965248878834	492	UVM_INFO @ 1319055586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all	41392120857854108234579038650785386941579144312294395452725888753933897313662	537	UVM_INFO @ 10274471894 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	75851078266283418861246939862741488183658741841892101936010925208099406286554	624	UVM_INFO @ 742226057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	52654395038854465432214285496537457920064003800590217125091073518255842545248	301	UVM_INFO @ 228426266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	97992044185278596123310170662538624783231815715896526893269185043219771660701	822	UVM_INFO @ 3757496488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_post_trans	96133201089948749167846227889741889901858036985150314672401647176481610774267	324	UVM_INFO @ 318129047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	65631734362929623327662916303093022492263780683660323744129851858947000235117	966	UVM_INFO @ 7337864027 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	39118470311218696462561134556302679151465443458001061661533530870037319895098	178	UVM_INFO @ 47933892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	92910075620432211720122521353985165538117604085273891671789879886563750779150	436	UVM_INFO @ 562382972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	95467018875203555471219187011210049777975559469819052687671609608896710985699	175	UVM_INFO @ 41770911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	19246733464987250462804115392654987578251103367584235527268325491391772310031	314	UVM_INFO @ 279919603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	64923208599324080666872871449301015838132264336948001681587688647499481026501	176	UVM_INFO @ 35419798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_state_failure	48148604494086349673624277238267627666842545560458807076223875976512325924937	1875	UVM_INFO @ 2134420329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error				9 test runs
	lc_ctrl_stress_all	92418499759869960852798819179484127650737188609475079411353037602378297968174	922	UVM_INFO @ 3744459247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	766246924317606160413512757113941693856558523939034979735011869341686190357	362	UVM_INFO @ 1380875803 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	81884643401369147051741961118866881940595351102838294366209084676584553235548	195	UVM_INFO @ 119296904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	53301595555588773720852335041018543599111125824462618432694935565238865478844	197	UVM_INFO @ 246747322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	10902940082277404029741682053645096583715077883894950280323368239512498697780	1988	UVM_INFO @ 1442298989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	9518993356036311809410691781199687701002251262811431113370623847762714923072	1474	UVM_INFO @ 11436896058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	26461294636942577399761358684169197574544174755725487353697053880066446845819	195	UVM_INFO @ 162180303 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_errors	87475709160789945820069766030549473854721999279994758578379403569144266689694	569	UVM_INFO @ 607993865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_jtag_prog_failure	115271554179526192750750768099372231258529416874824064007869375709303801471385	313	UVM_INFO @ 195090038 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				6 test runs
	lc_ctrl_stress_all_with_rand_reset	20435830314138339623678095632276143932827891782581851036502893938158210556371	284	UVM_INFO @ 569381558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	14286876721793165271660249827258646750785775598255316875185930596004253432019	599	UVM_INFO @ 4188411386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	73028365543516712372267701460699504619864148154866640192075487955790822270368	4799	UVM_INFO @ 6597506911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	5806925677342175118620494836355499478785288352416982329435607878345392368745	167	UVM_INFO @ 1491398426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	41659861069918684133206364908157584362869398647977289099804268537198633451866	3845	UVM_INFO @ 56382462320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	lc_ctrl_stress_all_with_rand_reset	108560141008918798766152439639831115947816977847670114382321462650605923289917	1816	UVM_INFO @ 9613937357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:933) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly.				1 test run
	lc_ctrl_stress_all_with_rand_reset	6080452158291567608807864901238524070730678484954068486337241183293675847654	2442	UVM_INFO @ 5404865954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---