Simulation Results: lc_ctrl/volatile_unlock_enabled

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.66 %
  • code
  • 94.15 %
  • assert
  • 96.83 %
  • func
  • 90.00 %
  • block
  • 97.11 %
  • line
  • 97.69 %
  • branch
  • 92.68 %
  • toggle
  • 88.60 %
  • FSM
  • 97.62 %
Validation stages
V1
100.00%
V2
94.85%
V2S
96.00%
V3
20.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 20 20 100.00
lc_ctrl_smoke 3.000s 1096.608us 20 20 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.000s 17.982us 1 1 100.00
csr_rw 5 5 100.00
lc_ctrl_csr_rw 2.000s 57.505us 5 5 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.000s 205.797us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 2.000s 27.384us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 2.000s 137.530us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
lc_ctrl_csr_rw 2.000s 57.505us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 27.384us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 20 20 100.00
lc_ctrl_state_post_trans 4.000s 123.401us 20 20 100.00
regwen_during_op 10 10 100.00
lc_ctrl_regwen_during_op 10.000s 351.805us 10 10 100.00
rand_wr_claim_transition_if 10 10 100.00
lc_ctrl_claim_transition_if 2.000s 64.266us 10 10 100.00
lc_prog_failure 20 20 100.00
lc_ctrl_prog_failure 4.000s 579.938us 20 20 100.00
lc_state_failure 20 20 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_errors 20 20 100.00
lc_ctrl_errors 7.000s 1180.379us 20 20 100.00
security_escalation 128 140 91.43
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_prog_failure 4.000s 579.938us 20 20 100.00
lc_ctrl_errors 7.000s 1180.379us 20 20 100.00
lc_ctrl_security_escalation 7.000s 1724.410us 20 20 100.00
lc_ctrl_jtag_state_failure 22.000s 1965.284us 13 20 65.00
lc_ctrl_jtag_prog_failure 7.000s 604.309us 17 20 85.00
lc_ctrl_jtag_errors 26.000s 16857.689us 18 20 90.00
jtag_access 199 210 94.76
lc_ctrl_jtag_smoke 6.000s 5071.690us 20 20 100.00
lc_ctrl_jtag_state_post_trans 9.000s 1338.925us 14 20 70.00
lc_ctrl_jtag_prog_failure 7.000s 604.309us 17 20 85.00
lc_ctrl_jtag_errors 26.000s 16857.689us 18 20 90.00
lc_ctrl_jtag_access 14.000s 1385.988us 50 50 100.00
lc_ctrl_jtag_regwen_during_op 11.000s 1263.946us 10 10 100.00
lc_ctrl_jtag_csr_hw_reset 3.000s 76.938us 10 10 100.00
lc_ctrl_jtag_csr_rw 3.000s 82.577us 10 10 100.00
lc_ctrl_jtag_csr_bit_bash 17.000s 12002.810us 10 10 100.00
lc_ctrl_jtag_csr_aliasing 4.000s 576.284us 10 10 100.00
lc_ctrl_jtag_same_csr_outstanding 2.000s 64.176us 10 10 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.000s 131.821us 10 10 100.00
lc_ctrl_jtag_alert_test 2.000s 1812.943us 10 10 100.00
jtag_priority 9 10 90.00
lc_ctrl_jtag_priority 11.000s 1520.382us 9 10 90.00
lc_ctrl_volatile_unlock 10 10 100.00
lc_ctrl_volatile_unlock_smoke 2.000s 115.015us 10 10 100.00
stress_all 7 10 70.00
lc_ctrl_stress_all 207.000s 79265.709us 7 10 70.00
alert_test 10 10 100.00
lc_ctrl_alert_test 2.000s 114.153us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 545.754us 25 25 100.00
tl_d_illegal_access 25 25 100.00
lc_ctrl_tl_errors 4.000s 545.754us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.000s 17.982us 1 1 100.00
lc_ctrl_csr_rw 2.000s 57.505us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 27.384us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 290.405us 5 5 100.00
tl_d_partial_access 12 12 100.00
lc_ctrl_csr_hw_reset 1.000s 17.982us 1 1 100.00
lc_ctrl_csr_rw 2.000s 57.505us 5 5 100.00
lc_ctrl_csr_aliasing 2.000s 27.384us 1 1 100.00
lc_ctrl_same_csr_outstanding 2.000s 290.405us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
lc_ctrl_tl_intg_err 3.000s 1562.016us 25 25 100.00
sec_cm_bus_integrity 25 25 100.00
lc_ctrl_tl_intg_err 3.000s 1562.016us 25 25 100.00
sec_cm_transition_config_regwen 10 10 100.00
lc_ctrl_regwen_during_op 10.000s 351.805us 10 10 100.00
sec_cm_manuf_state_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
sec_cm_transition_ctr_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
sec_cm_manuf_state_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
sec_cm_transition_ctr_bkgn_chk 25 25 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
sec_cm_state_config_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
sec_cm_main_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
sec_cm_kmac_fsm_sparse 25 25 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
sec_cm_main_fsm_local_esc 25 25 100.00
lc_ctrl_state_failure 7.000s 834.905us 20 20 100.00
lc_ctrl_sec_cm 4.000s 920.219us 5 5 100.00
sec_cm_main_fsm_global_esc 20 20 100.00
lc_ctrl_security_escalation 7.000s 1724.410us 20 20 100.00
sec_cm_main_ctrl_flow_consistency 34 40 85.00
lc_ctrl_state_post_trans 4.000s 123.401us 20 20 100.00
lc_ctrl_jtag_state_post_trans 9.000s 1338.925us 14 20 70.00
sec_cm_intersig_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.000s 12397.804us 10 10 100.00
sec_cm_token_valid_ctrl_mubi 10 10 100.00
lc_ctrl_sec_mubi 8.000s 12397.804us 10 10 100.00
sec_cm_token_digest 10 10 100.00
lc_ctrl_sec_token_digest 8.000s 2397.467us 10 10 100.00
sec_cm_token_mux_ctrl_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 701.263us 10 10 100.00
sec_cm_token_valid_mux_redun 10 10 100.00
lc_ctrl_sec_token_mux 9.000s 701.263us 10 10 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 10 20.00
lc_ctrl_stress_all_with_rand_reset 57.000s 32298.519us 2 10 20.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_state_error has unexpected timeout error 17 test runs
lc_ctrl_jtag_state_failure 75522466725993314307288135776951993208947637595024373064325098082638334609953 512
UVM_INFO @ 752761236 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 53508682727881312749207788567091359305166162633192442061571695026305051326582 578
UVM_INFO @ 271436727 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 109905659079794766150655299958424767193419933190706364972767323885031227189323 420
UVM_INFO @ 2190456777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 5031642181260465302048881829260658258064783620854528505015551159024544103512 3324
UVM_INFO @ 22070236433 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 72225204181776795251221025355738273938200982530770963485174626000780049790334 217
UVM_INFO @ 962430536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 90006381398496845458136781927935204051899637427465619185630401313620290189009 336
UVM_INFO @ 350873249 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 101486299676405058248679793280949074310650236624150887648646871418931248176809 433
UVM_INFO @ 339578795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 87065513655652767072768797414533205070389456829073813657547254049475446042675 433
UVM_INFO @ 394410155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 44740609534976541900740448339982600487475154269918340324931528547472938844868 175
UVM_INFO @ 64385504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 91218137818430939199518719865085581278723159600214780662560606920486910939202 728
UVM_INFO @ 5324270106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 9890788089182943137999272105801828350176438468077356858937807890711716025179 199
UVM_INFO @ 506765209 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 88570846570514239999007034181608791939380999253496548575800317227136647386745 1372
UVM_INFO @ 2180183124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 59887346613161270172947488100409700110971265601120950493109182938131809106688 175
UVM_INFO @ 29773275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 102180862241006190723851971535832238841306832320493432980976669815285031599817 200
UVM_INFO @ 400832430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 3303177358655059105167356624826014174397620498133459856964916599326116885023 274
UVM_INFO @ 942774612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_post_trans 48212912509471994208848360643845994270984853446526136423561643603318518423282 198
UVM_INFO @ 307719240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_state_failure 26893240536886495359240523925315503433448387755046772558637716063125963068552 199
UVM_INFO @ 2250616272 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal_prog_error has unexpected timeout error 7 test runs
lc_ctrl_jtag_prog_failure 58040377656632282047828650747496730271097164176260526765931397251153181615152 355
UVM_INFO @ 1570300289 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 61509429455312170499137994940603985969808758665453640745285941439578432336551 176
UVM_INFO @ 46106855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 1320994588803225996595730654157651201888102801542316780026214899203650409668 5354
UVM_INFO @ 14869087886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all 14359191496254231465222604183101339970393899898798276882933996751097409689570 1061
UVM_INFO @ 11392962636 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 82584299375257046119954198190230725543707440115655630632876325593571224174045 216
UVM_INFO @ 114555603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_prog_failure 108640063635343637137536378859495301558426005027104373155502068891601061678992 234
UVM_INFO @ 149840980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 91900774688998952514419183389091871065663052115431436609693913329953561767204 365
UVM_INFO @ 403190475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1297) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 5 test runs
lc_ctrl_stress_all_with_rand_reset 19384549570727298245279236526898515436404936944407552598500662163668115255769 1562
UVM_INFO @ 1685903375 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 11518048083932707171296910838426052979627007038351743523205088263829992086599 1542
UVM_INFO @ 32298518895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 50313439416254048685939355944927319403183209019685008721907875581561784005755 365
UVM_INFO @ 2723628509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 61709189121774425811271779110755955970542144388893627555970075575599242173908 5364
UVM_INFO @ 9394432148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_stress_all_with_rand_reset 104201209003716422201883429459987377236701052821911001566920653639966096286273 730
UVM_INFO @ 682233293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (lc_ctrl_jtag_priority_vseq.sv:113) [lc_ctrl_jtag_priority_vseq] timeout occurred! 1 test run
lc_ctrl_jtag_priority 107533824755154750377366542568591144425313782438411132011523077243185464367127 157
UVM_INFO @ 10015798571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---