Simulation Results: otbn

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.66 %
  • code
  • 87.00 %
  • assert
  • 96.97 %
  • func
  • 100.00 %
  • block
  • 99.31 %
  • line
  • 99.52 %
  • branch
  • 94.86 %
  • toggle
  • 86.01 %
  • FSM
  • 67.61 %
Validation stages
V1
100.00%
V2
94.71%
V2S
96.66%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
otbn_smoke 15.000s 113.747us 1 1 100.00
otbn_smoke_vectorized 8.000s 22.503us 1 1 100.00
single_binary 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 10.000s 61.165us 1 1 100.00
csr_rw 5 5 100.00
otbn_csr_rw 10.000s 25.492us 5 5 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 12.000s 350.387us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 9.000s 55.225us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
otbn_csr_mem_rw_with_rand_reset 13.000s 146.437us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
otbn_csr_rw 10.000s 25.492us 5 5 100.00
otbn_csr_aliasing 9.000s 55.225us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 74.000s 3025.660us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 31.000s 640.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 10 10 100.00
otbn_reset 38.000s 105.282us 10 10 100.00
multi_error 1 1 100.00
otbn_multi_err 65.000s 774.275us 1 1 100.00
wfi 2 7 28.57
otbn_wfi_smoke 5.000s 53.234us 0 1 0.00
otbn_wfi_sec_wipe 8.000s 13.577us 2 5 40.00
otbn_wfi_back_to_back 6.000s 7.017us 0 1 0.00
back_to_back 10 10 100.00
otbn_multi 99.000s 330.614us 10 10 100.00
stress_all 10 10 100.00
otbn_stress_all 348.000s 858.186us 10 10 100.00
lc_escalation 56 60 93.33
otbn_escalate 24.000s 96.551us 56 60 93.33
zero_state_err_urnd 5 5 100.00
otbn_zero_state_err_urnd 10.000s 21.227us 5 5 100.00
sw_errs_fatal_chk 10 10 100.00
otbn_sw_errs_fatal_chk 29.000s 288.871us 10 10 100.00
alert_test 10 10 100.00
otbn_alert_test 13.000s 21.150us 10 10 100.00
intr_test 10 10 100.00
otbn_intr_test 5.000s 20.454us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
otbn_tl_errors 11.000s 161.619us 25 25 100.00
tl_d_illegal_access 25 25 100.00
otbn_tl_errors 11.000s 161.619us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
otbn_csr_hw_reset 10.000s 61.165us 1 1 100.00
otbn_csr_rw 10.000s 25.492us 5 5 100.00
otbn_csr_aliasing 9.000s 55.225us 1 1 100.00
otbn_same_csr_outstanding 6.000s 95.495us 5 5 100.00
tl_d_partial_access 12 12 100.00
otbn_csr_hw_reset 10.000s 61.165us 1 1 100.00
otbn_csr_rw 10.000s 25.492us 5 5 100.00
otbn_csr_aliasing 9.000s 55.225us 1 1 100.00
otbn_same_csr_outstanding 6.000s 95.495us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 25 25 100.00
otbn_imem_err 15.000s 49.887us 10 10 100.00
otbn_dmem_err 16.000s 461.613us 15 15 100.00
internal_integrity 15 17 88.24
otbn_alu_bignum_mod_err 30.000s 170.880us 5 5 100.00
otbn_controller_ispr_rdata_err 15.000s 151.137us 5 5 100.00
otbn_mac_bignum_acc_err 13.000s 121.254us 5 5 100.00
otbn_urnd_err 7.000s 5.739us 0 2 0.00
illegal_bus_access 5 5 100.00
otbn_illegal_mem_acc 7.000s 17.466us 5 5 100.00
otbn_mem_gnt_acc_err 2 2 100.00
otbn_mem_gnt_acc_err 8.000s 20.948us 2 2 100.00
otbn_non_sec_partial_wipe 9 10 90.00
otbn_partial_wipe 11.000s 50.833us 9 10 90.00
tl_intg_err 30 30 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
otbn_tl_intg_err 34.000s 209.695us 25 25 100.00
passthru_mem_tl_intg_err 4 5 80.00
otbn_passthru_mem_tl_intg_err 74.000s 275.244us 4 5 80.00
prim_fsm_check 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
prim_count_check 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 15.000s 113.747us 1 1 100.00
sec_cm_data_mem_integrity 15 15 100.00
otbn_dmem_err 16.000s 461.613us 15 15 100.00
sec_cm_instruction_mem_integrity 10 10 100.00
otbn_imem_err 15.000s 49.887us 10 10 100.00
sec_cm_bus_integrity 25 25 100.00
otbn_tl_intg_err 34.000s 209.695us 25 25 100.00
sec_cm_controller_fsm_global_esc 56 60 93.33
otbn_escalate 24.000s 96.551us 56 60 93.33
sec_cm_controller_fsm_local_esc 40 40 100.00
otbn_imem_err 15.000s 49.887us 10 10 100.00
otbn_dmem_err 16.000s 461.613us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 21.227us 5 5 100.00
otbn_illegal_mem_acc 7.000s 17.466us 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_controller_fsm_sparse 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_scramble_key_sideload 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
sec_cm_scramble_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 15.000s 49.887us 10 10 100.00
otbn_dmem_err 16.000s 461.613us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 21.227us 5 5 100.00
otbn_illegal_mem_acc 7.000s 17.466us 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_scramble_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 56 60 93.33
otbn_escalate 24.000s 96.551us 56 60 93.33
sec_cm_start_stop_ctrl_fsm_local_esc 40 40 100.00
otbn_imem_err 15.000s 49.887us 10 10 100.00
otbn_dmem_err 16.000s 461.613us 15 15 100.00
otbn_zero_state_err_urnd 10.000s 21.227us 5 5 100.00
otbn_illegal_mem_acc 7.000s 17.466us 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_start_stop_ctrl_fsm_sparse 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_data_reg_sw_sca 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
sec_cm_ctrl_redun 12 12 100.00
otbn_ctrl_redun 13.000s 47.547us 12 12 100.00
sec_cm_pc_ctrl_flow_redun 5 5 100.00
otbn_pc_ctrl_flow_redun 10.000s 30.295us 5 5 100.00
sec_cm_rnd_bus_consistency 5 5 100.00
otbn_rnd_sec_cm 78.000s 146.605us 5 5 100.00
sec_cm_rnd_rng_digest 5 5 100.00
otbn_rnd_sec_cm 78.000s 146.605us 5 5 100.00
sec_cm_rf_base_data_reg_sw_integrity 10 10 100.00
otbn_rf_base_intg_err 12.000s 26.213us 10 10 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_stack_wr_ptr_ctr_redun 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 8 10 80.00
otbn_rf_bignum_intg_err 19.000s 86.223us 8 10 80.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_loop_stack_ctr_redun 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
sec_cm_loop_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 12.000s 19.999us 4 5 80.00
sec_cm_call_stack_addr_integrity 4 5 80.00
otbn_stack_addr_integ_chk 12.000s 19.999us 4 5 80.00
sec_cm_start_stop_ctrl_state_consistency 7 7 100.00
otbn_sec_wipe_err 11.000s 32.850us 7 7 100.00
sec_cm_data_mem_sec_wipe 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
sec_cm_instruction_mem_sec_wipe 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
sec_cm_data_reg_sw_sec_wipe 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
sec_cm_write_mem_integrity 10 10 100.00
otbn_multi 99.000s 330.614us 10 10 100.00
sec_cm_ctrl_flow_count 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
sec_cm_ctrl_flow_sca 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
sec_cm_data_mem_sw_noaccess 5 5 100.00
otbn_sw_no_acc 10.000s 44.193us 5 5 100.00
sec_cm_key_sideload 100 100 100.00
otbn_single 133.000s 900.061us 100 100 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
otbn_sec_cm 412.000s 7492.405us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
otbn_stress_all_with_rand_reset 20.000s 437.058us 0 10 0.00

Error Messages

   Test seed line log context
UVM_FATAL sequencer [SEQDEFPRI] Sequence parent_sequence has illegal priority: -* 9 test runs
otbn_stress_all_with_rand_reset 50182680363155257786190448309752422704869275552453580113188761332143291160616 153
UVM_INFO @ 32238234 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 24667818960169617684809124699362053002730108307640949723131901170790377074307 160
UVM_INFO @ 291434796 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 7633170012667390493008164261383746624498638624292323872111069367919035178535 152
UVM_INFO @ 41593339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 95779238321508455701705488696196702772025025601582205268386307866454567092268 152
UVM_INFO @ 16876496 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 57992023297808227910220951922218714725584260708277896897028192111927478147488 151
UVM_INFO @ 63075976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 39380193618417000259984803859551044658730032962609105846508713754631817159782 150
UVM_INFO @ 58015528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 1801293217669272237661922498410862637099409455753509614490553848266803260158 158
UVM_INFO @ 35196378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 24592211544794441459316515318176699133285200295495010529622277128499217805145 163
UVM_INFO @ 437058293 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all_with_rand_reset 32503145319148386330386821171471916400525504235180452205016635219402891371584 147
UVM_INFO @ 56463916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_sva_*/otbn_idle_checker.sv,196): Assertion NotRunningWhenLocked_A has failed 3 test runs
otbn_urnd_err 48742741722490360913729527168459107997969380874401808825402494006749918904228 109
UVM_ERROR @ 5738870 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 5738870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_urnd_err 69940231661966903411781308335544504061715617760032614775575141056690218684798 111
UVM_ERROR @ 23144405 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 23144405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_partial_wipe 67947071842979087046138093612933914686710490574775315725626129202459395529184 110
UVM_ERROR @ 11525630 ps: (otbn_idle_checker.sv:196) [ASSERT FAILED] NotRunningWhenLocked_A
UVM_INFO @ 11525630 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,EILLEN: (File: /nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_env_cov.sv, Line: *):(Time: * PS + *) Sampled value (*) for coverpoint (worklib.otbn_env_pkg::otbn_env_cov::pairwise_insn_cg@*_*.cur_cp) is an illegal value. 3 test runs
otbn_wfi_sec_wipe 55534721108495924463022167853925562355157670826329855027547641065690240039019 111
UVM_FATAL @ 4345344 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 4345344 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_sec_wipe 92384096836541167767291829600803608361078248748139895680242162672512012013607 112
UVM_FATAL @ 55977523 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 55977523 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_sec_wipe 107560861976907896552568165891381138251144712259292240796424109187126660849361 115
UVM_FATAL @ 69008207 ps: (otbn_env_cov.sv:2728) [uvm_test_top.env.cov] Unknown encoding () for instruction `wfi'
UVM_INFO @ 69008207 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:440) [scoreboard] Check failed model_status == * (* [*] vs * [*]) Saw instruction when not in BUSY_EXECUTE operational state. 2 test runs
otbn_wfi_smoke 91540361659982110656050024529680847788316922381934806035837958666086209392908 114
UVM_INFO @ 53234386 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_wfi_back_to_back 2177948927646688406676434203897619382473884598721274333094206145649283399111 113
UVM_INFO @ 7017394 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_*/otbn_model_if.sv,158): Assertion NoModelErrs has failed 2 test runs
otbn_escalate 110263396893276251117147324663099432405941250606127017952068205599977835169001 115
UVM_ERROR @ 135765681 ps: (otbn_model_if.sv:158) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 135765681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_escalate 56302152016773863034829112624664245384784323708273035409665655236803980449559 118
UVM_ERROR @ 61757437 ps: (otbn_model_if.sv:158) [ASSERT FAILED] NoModelErrs
UVM_INFO @ 61757437 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_rf_bignum_intg_err 65946735102653582713948504826217131037231525694945410812602164838041140255591 115
UVM_INFO @ 280553728 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_rf_bignum_intg_err 53052431776352849251129504371496071732568322027084292035542350932456832714097 114
UVM_INFO @ 108468560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. 1 test run
otbn_passthru_mem_tl_intg_err 28396259014833950068406312149643027586943739188818587151915949518586332335660 86
UVM_INFO @ 2497871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 59243671835705976204488344635954748189067103073032233512352995807291502104731 117
UVM_ERROR @ 24790175 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 24790175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:551) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a recov alert but it still hasn't arrived. 1 test run
otbn_escalate 67411336093768778782250974564809186676769130004099552423850693995898506740884 106
UVM_INFO @ 13461637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_stress_all_with_rand_reset 4794561077865985607207801490347967432177376156302934426613293632645861220881 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1
UVM_ERROR (otbn_scoreboard.sv:322) [scoreboard] Check failed item.d_data == exp_read_data.val (* [*] vs * [*]) value for register otbn_reg_block.status 1 test run
otbn_escalate 58488991488203664142112546206906755698946969689364786278146882514630933809237 105
UVM_INFO @ 2880322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---