Simulation Results: rom_ctrl/32kb

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.67 %
  • code
  • 90.19 %
  • assert
  • 97.53 %
  • func
  • 99.29 %
  • block
  • 89.78 %
  • line
  • 91.66 %
  • branch
  • 84.42 %
  • toggle
  • 84.69 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
94.37%
V2S
98.31%
V3
35.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 3.000s 405.946us 2 2 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.000s 216.554us 1 1 100.00
csr_rw 5 5 100.00
rom_ctrl_csr_rw 2.000s 66.704us 5 5 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 2.000s 353.132us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 2.000s 59.025us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.000s 56.692us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rom_ctrl_csr_rw 2.000s 66.704us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 59.025us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 2.000s 55.651us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 2.000s 70.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 3.000s 911.738us 0 2 0.00
stress_all 18 20 90.00
rom_ctrl_stress_all 12.000s 759.040us 18 20 90.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 5.000s 396.449us 2 2 100.00
alert_test 10 10 100.00
rom_ctrl_alert_test 3.000s 75.912us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rom_ctrl_tl_errors 6.000s 377.860us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rom_ctrl_tl_errors 6.000s 377.860us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 216.554us 1 1 100.00
rom_ctrl_csr_rw 2.000s 66.704us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 59.025us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 72.833us 5 5 100.00
tl_d_partial_access 12 12 100.00
rom_ctrl_csr_hw_reset 4.000s 216.554us 1 1 100.00
rom_ctrl_csr_rw 2.000s 66.704us 5 5 100.00
rom_ctrl_csr_aliasing 2.000s 59.025us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.000s 72.833us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
passthru_mem_tl_intg_err 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.000s 2209.021us 5 5 100.00
tl_intg_err 30 30 100.00
rom_ctrl_sec_cm 141.000s 1445.743us 5 5 100.00
rom_ctrl_tl_intg_err 37.000s 370.981us 25 25 100.00
prim_fsm_check 5 5 100.00
rom_ctrl_sec_cm 141.000s 1445.743us 5 5 100.00
prim_count_check 5 5 100.00
rom_ctrl_sec_cm 141.000s 1445.743us 5 5 100.00
sec_cm_checker_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
sec_cm_checker_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
sec_cm_checker_fsm_local_esc 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
sec_cm_compare_ctrl_flow_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
sec_cm_compare_ctr_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
sec_cm_compare_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 141.000s 1445.743us 5 5 100.00
sec_cm_fsm_sparse 5 5 100.00
rom_ctrl_sec_cm 141.000s 1445.743us 5 5 100.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 3.000s 405.946us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 3.000s 405.946us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 3.000s 405.946us 2 2 100.00
sec_cm_bus_integrity 25 25 100.00
rom_ctrl_tl_intg_err 37.000s 370.981us 25 25 100.00
sec_cm_bus_local_esc 21 22 95.45
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
rom_ctrl_kmac_err_chk 5.000s 396.449us 2 2 100.00
sec_cm_mux_mubi 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
sec_cm_mux_consistency 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
sec_cm_ctrl_redun 19 20 95.00
rom_ctrl_corrupt_sig_fatal_chk 44.000s 18307.452us 19 20 95.00
sec_cm_ctrl_mem_integrity 5 5 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.000s 2209.021us 5 5 100.00
sec_cm_tlul_fifo_ctr_redun 5 5 100.00
rom_ctrl_sec_cm 141.000s 1445.743us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 7 20 35.00
rom_ctrl_stress_all_with_rand_reset 55.000s 15566.326us 7 20 35.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:480) scoreboard [scoreboard] Waited * cycles but did not see alert fatal. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 12 test runs
rom_ctrl_stress_all_with_rand_reset 98168688932799754218119610468810328220660803255100712937751254420668993470093 153
UVM_INFO @ 2714182124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 53066540641776246855664926830914000934772457110701662382128575772931104303584 128
UVM_INFO @ 4987705648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 22323250404413250286379116405694640452394166129010801448789816117695140359858 94
UVM_INFO @ 3374810729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 44321284300008516147632863349471390911551552496678486919533653738140934586984 90
UVM_INFO @ 477091991 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 22810988720888333380237848849579171926297614933730438074324637597319496441995 108
UVM_INFO @ 1823387978 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 63094098553579598967254670500609302289009457497461814374884233354264683271091 90
UVM_INFO @ 505115768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 21173241968092125725856208027091834356147324606656568816896899154804451522951 114
UVM_INFO @ 2164592408 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 29864747660467696313100672219300357980288835798794511874302181252922235133471 106
UVM_INFO @ 2335949760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 103505823106112248015486834832205421973209814246554318695806603106510450172517 121
UVM_INFO @ 549994693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all 85594674972220834794740864350670605625158081816127545397778201862230695325619 88
UVM_INFO @ 495579972 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 49647603664645638832542340290667102136283151585329318500351214877675668925955 107
UVM_INFO @ 827161173 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 15039225937024851200526087550865519357251486166430125772228606919151799134728 105
UVM_INFO @ 2244998305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 2 test runs
rom_ctrl_max_throughput_chk 88160588929293389009481444932857516230450466131147846787776856660960925470173 88
UVM_INFO @ 911738190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_max_throughput_chk 10498242156454501955928720293522818814624480535617763938344523333685902122941 88
UVM_INFO @ 166395836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1059) virtual_sequencer [rom_ctrl_kmac_err_chk_vseq] Expected alert (fatal) did not fire in * cycles. 2 test runs
rom_ctrl_stress_all 103344773041129484404873638127788633069818571059328010715954201165500161322992 87
UVM_INFO @ 5117589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_ctrl_stress_all_with_rand_reset 101152285437314315664314574765741841653939409780686081607946822036317357468727 185
UVM_INFO @ 15566325790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:465) [rom_ctrl_common_vseq] wait timeout occurred! 1 test run
rom_ctrl_stress_all_with_rand_reset 19319914543282957215085949853654018876979210030888537500529041553518255862616 119
UVM_INFO @ 10957943783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:256) scoreboard [scoreboard] alert fatal has unexpected timeout error 1 test run
rom_ctrl_corrupt_sig_fatal_chk 90087505918288238001658646976238384455411559349605883392055469105640797921008 88
UVM_INFO @ 342632150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---