Simulation Results: rstmgr

 
18/09/2026 15:01:41 DVSim: v1.49.0 sha: 3823b79 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.93 %
  • code
  • 99.59 %
  • assert
  • 98.72 %
  • func
  • 98.49 %
  • line
  • 99.19 %
  • branch
  • 99.72 %
  • cond
  • 99.43 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
98.57%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 5 5 100.00
rstmgr_smoke 1.720s 64.415us 5 5 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.570s 93.276us 1 1 100.00
csr_rw 5 5 100.00
rstmgr_csr_rw 1.290s 39.814us 5 5 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 3.880s 81.489us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.380s 39.054us 1 1 100.00
csr_mem_rw_with_rand_reset 5 5 100.00
rstmgr_csr_mem_rw_with_rand_reset 2.450s 95.874us 5 5 100.00
regwen_csr_and_corresponding_lockable_csr 6 6 100.00
rstmgr_csr_rw 1.290s 39.814us 5 5 100.00
rstmgr_csr_aliasing 1.380s 39.054us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 5 5 100.00
rstmgr_por_stretcher 2.040s 133.766us 5 5 100.00
sw_rst 5 5 100.00
rstmgr_sw_rst 1.490s 38.592us 5 5 100.00
sw_rst_reset_race 5 5 100.00
rstmgr_sw_rst_reset_race 1.540s 76.501us 5 5 100.00
reset_info 5 5 100.00
rstmgr_reset 8.500s 736.552us 5 5 100.00
cpu_info 5 5 100.00
rstmgr_reset 8.500s 736.552us 5 5 100.00
alert_info 5 5 100.00
rstmgr_reset 8.500s 736.552us 5 5 100.00
reset_info_capture 5 5 100.00
rstmgr_reset 8.500s 736.552us 5 5 100.00
stress_all 5 5 100.00
rstmgr_stress_all 34.260s 3080.404us 5 5 100.00
alert_test 10 10 100.00
rstmgr_alert_test 1.400s 42.414us 10 10 100.00
tl_d_oob_addr_access 25 25 100.00
rstmgr_tl_errors 3.450s 92.300us 25 25 100.00
tl_d_illegal_access 25 25 100.00
rstmgr_tl_errors 3.450s 92.300us 25 25 100.00
tl_d_outstanding_access 12 12 100.00
rstmgr_csr_hw_reset 1.570s 93.276us 1 1 100.00
rstmgr_csr_rw 1.290s 39.814us 5 5 100.00
rstmgr_csr_aliasing 1.380s 39.054us 1 1 100.00
rstmgr_same_csr_outstanding 1.490s 71.917us 5 5 100.00
tl_d_partial_access 12 12 100.00
rstmgr_csr_hw_reset 1.570s 93.276us 1 1 100.00
rstmgr_csr_rw 1.290s 39.814us 5 5 100.00
rstmgr_csr_aliasing 1.380s 39.054us 1 1 100.00
rstmgr_same_csr_outstanding 1.490s 71.917us 5 5 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 30 30 100.00
rstmgr_sec_cm 54.950s 8330.936us 5 5 100.00
rstmgr_tl_intg_err 7.540s 652.175us 25 25 100.00
prim_count_check 5 5 100.00
rstmgr_sec_cm 54.950s 8330.936us 5 5 100.00
prim_fsm_check 5 5 100.00
rstmgr_sec_cm 54.950s 8330.936us 5 5 100.00
sec_cm_bus_integrity 25 25 100.00
rstmgr_tl_intg_err 7.540s 652.175us 25 25 100.00
sec_cm_scan_intersig_mubi 5 5 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.720s 67.884us 5 5 100.00
sec_cm_leaf_rst_bkgn_chk 24 25 96.00
rstmgr_leaf_rst_cnsty 6.650s 469.361us 24 25 96.00
sec_cm_leaf_rst_shadow 5 5 100.00
rstmgr_leaf_rst_shadow_attack 3.480s 291.648us 5 5 100.00
sec_cm_leaf_fsm_sparse 5 5 100.00
rstmgr_sec_cm 54.950s 8330.936us 5 5 100.00
sec_cm_sw_rst_config_regwen 5 5 100.00
rstmgr_csr_rw 1.290s 39.814us 5 5 100.00
sec_cm_dump_ctrl_config_regwen 5 5 100.00
rstmgr_csr_rw 1.290s 39.814us 5 5 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:474) scoreboard [scoreboard] Waited * cycles but did not see alert fatal_cnsty_fault. (Max wait calculated ALERT_B2B_DELAY + max_delay + * = * + * + *) 1 test run
rstmgr_leaf_rst_cnsty 74338816384571704079632759883308277332978078437678355345608003072357216825227 83
UVM_INFO @ 29582915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---